Patents by Inventor Arash Farhoodfar
Arash Farhoodfar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200014407Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: ApplicationFiled: September 18, 2019Publication date: January 9, 2020Applicant: INPHI CORPORATIONInventors: Benjamin SMITH, Arash FARHOODFAR, Stewart CROZIER, Frank R. KSCHISCHANG, Andrew HUNT
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Patent number: 10461781Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.Type: GrantFiled: June 18, 2018Date of Patent: October 29, 2019Assignee: INPHI CORPORATIONInventors: Benjamin Smith, Arash Farhoodfar, Stewart Crozier, Frank R. Kschischang, Andrew Hunt
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Publication number: 20190319741Abstract: An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.Type: ApplicationFiled: June 25, 2019Publication date: October 17, 2019Inventors: Benjamin P. SMITH, Arash FARHOODFAR
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Publication number: 20190305884Abstract: The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.Type: ApplicationFiled: June 18, 2019Publication date: October 3, 2019Inventors: Benjamin P. SMITH, Jamal RIANI, Arash FARHOODFAR, Sudeep BHOJA
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Publication number: 20190268091Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.Type: ApplicationFiled: May 3, 2019Publication date: August 29, 2019Inventors: Jamal RIANI, Benjamin P. SMITH, Volodymyr SHVYDUN, Sudeep BHOJA, Arash FARHOODFAR
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Patent number: 10374750Abstract: An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.Type: GrantFiled: October 9, 2018Date of Patent: August 6, 2019Assignee: INPHI CORPORATIONInventors: Benjamin P. Smith, Arash Farhoodfar
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Patent number: 10374752Abstract: The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.Type: GrantFiled: August 31, 2017Date of Patent: August 6, 2019Assignee: INPHI CORPORATIONInventors: Benjamin Smith, Jamal Riani, Arash Farhoodfar, Sudeep Bhoja
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Patent number: 10320425Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi?1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi?1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code.Type: GrantFiled: June 27, 2016Date of Patent: June 11, 2019Assignee: INPHI CORPORATIONInventors: Arash Farhoodfar, Frank R. Kschischang, Andrew Hunt, Benjamin P. Smith, John Lodge
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Publication number: 20190165806Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).Type: ApplicationFiled: January 30, 2019Publication date: May 30, 2019Inventors: Andre SZCZEPANEK, Arash FARHOODFAR, Sudeep BHOJA, Sean BATTY, Shaun LYTOLLIS
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Publication number: 20190158189Abstract: A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.Type: ApplicationFiled: January 28, 2019Publication date: May 23, 2019Inventors: Benjamin P. SMITH, Jamal RIANI, Sudeep BHOJA, Arash FARHOODFAR, Vipul BHATT
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Publication number: 20190132185Abstract: The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.Type: ApplicationFiled: December 26, 2018Publication date: May 2, 2019Inventors: Arash FARHOODFAR, Jitendra SWARNKAR, Michael DUCKERING, Andre SCZAPANEK, Scott FELLER, Shaun LYTOLLIS
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Patent number: 10236907Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).Type: GrantFiled: May 16, 2018Date of Patent: March 19, 2019Assignee: INPHI CORPORATIONInventors: Andre Szczepanek, Arash Farhoodfar, Sudeep Bhoja, Sean Batty, Shaun Lytollis
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Patent number: 10236994Abstract: A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.Type: GrantFiled: December 8, 2017Date of Patent: March 19, 2019Assignee: INPHI CORPORATIONInventors: Benjamin P. Smith, Jamal Riani, Sudeep Bhoja, Arash Farhoodfar, Vipul Bhatt
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Publication number: 20190068322Abstract: The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.Type: ApplicationFiled: August 31, 2017Publication date: February 28, 2019Inventors: Benjamin SMITH, Jamal RIANI, Arash FARHOODFAR, Sudeep BHOJA
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Publication number: 20190052513Abstract: The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.Type: ApplicationFiled: May 23, 2018Publication date: February 14, 2019Inventors: Arash FARHOODFAR, Jitendra SWARNKAR, Michael DUCKERING, Andre SCZAPANEK, Scott FELLER, Shaun LYTOLLIS
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Patent number: 10205625Abstract: The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.Type: GrantFiled: May 23, 2018Date of Patent: February 12, 2019Assignee: INPHI CORPORATIONInventors: Arash Farhoodfar, Jitendra Swarnkar, Michael Duckering, Andre Sczapanek, Scott Feller, Shaun Lytollis
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Publication number: 20190044653Abstract: An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.Type: ApplicationFiled: October 9, 2018Publication date: February 7, 2019Inventors: Benjamin P. SMITH, Arash FARHOODFAR
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Publication number: 20190020356Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.Type: ApplicationFiled: September 18, 2018Publication date: January 17, 2019Inventors: Arash FARHOODFAR, Frank R. KSCHISCHANG, Benjamin P. SMITH, Andrew HUNT
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Patent number: 10128980Abstract: An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.Type: GrantFiled: April 21, 2017Date of Patent: November 13, 2018Assignee: INPHI CORPORATIONInventors: Benjamin P. Smith, Arash Farhoodfar
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Patent number: 10110252Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.Type: GrantFiled: December 14, 2016Date of Patent: October 23, 2018Assignee: INPHI CORPORATIONInventors: Arash Farhoodfar, Frank R. Kschischang, Benjamin P. Smith, Andrew Hunt