Patents by Inventor Arichika Ishida

Arichika Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180003880
    Abstract: According to one embodiment, provided is a liquid crystal display device with a reduced size and little restriction for incorporation into other devices. The liquid crystal display device includes an array substrate that includes multiple thin film transistors for pixel driving, a scanning line and a signal line. The liquid crystal display device also includes a counter substrate disposed on the display side in a manner opposed to the array substrate. The liquid crystal display device further includes an FPC arranged to transmit an external signal for driving of the thin film transistors. One end portion of the FPC is connected to the scanning line and the signal line, while the other end portion is extended inward. The scanning line, the signal line and the FPC are disposed within an outline of the counter substrate.
    Type: Application
    Filed: September 14, 2017
    Publication date: January 4, 2018
    Applicant: Japan Display Inc.
    Inventors: Yoshiro AOKI, Yasushi KAWATA, Arichika ISHIDA
  • Publication number: 20170343845
    Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.
    Type: Application
    Filed: July 28, 2017
    Publication date: November 30, 2017
    Applicant: Japan Display Inc.
    Inventors: Yohei YAMAGUCHI, Arichika ISHIDA, Hidekazu MIYAKE, Hiroto MIYAKE, Isao SUZUMURA
  • Patent number: 9831349
    Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: November 28, 2017
    Assignee: Japan Display Inc.
    Inventors: Miyuki Ishikawa, Arichika Ishida, Masayoshi Fuchi, Hajime Watakabe, Takashi Okada
  • Patent number: 9804315
    Abstract: According to one embodiment, provided is a liquid crystal display device with a reduced size and little restriction for incorporation into other devices. The liquid crystal display device includes an array substrate that includes multiple thin film transistors for pixel driving. The liquid crystal display device also includes a counter substrate disposed in a manner opposed to the array substrate. The liquid crystal display device further includes an FPC arranged to transmit an external signal for driving of the thin film transistors. One of the array substrate and the counter substrate has an outline larger than that of the other, disposed on the display side, and includes a connecting portion at a position not opposed to the other on the side opposite to the display side. At least one end portion of the FPC is connected to the connecting portion, while the other end portion extends inward.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: October 31, 2017
    Assignee: Japan Display Inc.
    Inventors: Yoshiro Aoki, Yasushi Kawata, Arichika Ishida
  • Patent number: 9780227
    Abstract: According to one embodiment, a thin-film transistor and a method of manufacturing the thin-film transistor provided herein achieve enhanced reliability by preventing a disconnection in a gate insulating film at a position corresponding to an end surface of an oxide semiconductor layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. The channel region is placed between the source region and the drain region. The gate insulating film covers the oxide semiconductor layer in a range from at least a part of an upper surface to an end surface continuous with the upper surface of the oxide semiconductor layer. The oxide semiconductor layer is formed so as to have an oxygen concentration that becomes lower from a top side to a bottom side and the end surface is inclined so as to diverge from the top side to the bottom side.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: October 3, 2017
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Masayoshi Fuchi, Hajime Watakabe, Takashi Okada, Arichika Ishida
  • Patent number: 9772536
    Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 26, 2017
    Assignee: JAPAN DISPLAY INC.
    Inventors: Yohei Yamaguchi, Arichika Ishida, Hidekazu Miyake, Hiroto Miyake, Isao Suzumura
  • Publication number: 20170207255
    Abstract: According to one embodiment, a display device includes an underlying insulation layer formed on a surface of a resin layer, and a thin-film transistor formed above the surface of the resin layer via the underlying insulation layer. The underlying insulation layer includes a three-layer multilayer structure of a first silicon oxide film, a silicon nitride film formed above the first silicon oxide film, and a second silicon oxide film formed above the silicon nitride film.
    Type: Application
    Filed: April 5, 2017
    Publication date: July 20, 2017
    Applicant: Japan Display Inc.
    Inventors: Masato HIRAMATSU, Yasushi KAWATA, Arichika ISHIDA
  • Patent number: 9696577
    Abstract: According to one embodiment, a reflective type liquid crystal display device provided can suppress light leakage into a thin film transistor due to entry of extraneous light. An array substrate includes a glass substrate, a plurality of thin film transistors, a plurality of pixel electrodes, and a metal film. The plurality of thin film transistors are provided to the glass substrate. The plurality of pixel electrodes are spaced apart from each other and driven by the thin film transistors. The plurality of pixel electrodes reflect extraneous light entering the reflective type display device from a counter substrate side. The metal film is provided between a gap between the pixel electrodes and each of the thin film transistors.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: July 4, 2017
    Assignee: Japan Display Inc.
    Inventors: Muneharu Akiyoshi, Kisako Ninomiya, Yasushi Kawata, Hirotaka Hayashi, Arichika Ishida
  • Publication number: 20170168334
    Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.
    Type: Application
    Filed: February 28, 2017
    Publication date: June 15, 2017
    Applicant: Japan Display Inc.
    Inventors: Yohei Yamaguchi, Arichika Ishida, Hidekazu Miyake, Hiroto Miyake, Isao Suzumura
  • Patent number: 9666599
    Abstract: According to one embodiment, a display device includes an underlying insulation layer formed on a surface of a resin layer, and a thin-film transistor formed above the surface of the resin layer via the underlying insulation layer. The underlying insulation layer includes a three-layer multilayer structure of a first silicon oxide film, a silicon nitride film formed above the first silicon oxide film, and a second silicon oxide film formed above the silicon nitride film.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: May 30, 2017
    Assignee: Japan Display Inc.
    Inventors: Masato Hiramatsu, Yasushi Kawata, Arichika Ishida
  • Patent number: 9660039
    Abstract: According to one embodiment, a thin-film transistor includes a semiconductor layer SC including a channel region, and a source region and a drain region on both sides of the channel region, a gate electrode GE, a first electrode SE connected to the source region via a first contact hole CH1, a second electrode DE connected to the drain region via a second contact hole CH2, a source line connected to the first electrode, and a drain line connected to the second electrode. A distance from the first and second contact holes to an end of the respective regions in a direction of a channel width is greater than or equal to 5 ?m and less than or equal to 30 ?m. The source line and the drain line extend in directions different from each other.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 23, 2017
    Assignee: Japan Display Inc.
    Inventors: Hidekazu Miyake, Arichika Ishida, Hiroto Miyake, Isao Suzumura, Yohei Yamaguchi
  • Patent number: 9647130
    Abstract: According to one embodiment, a display device includes a thin-film transistor. The thin-film transistor includes a gate electrode, an insulating layer disposed to superpose the gate electrode, and a semiconductor layer disposed on the insulating layer. The gate electrode is opposed to at least the semiconductor layer in part. The gate electrode includes a laminate including a first layer containing silicon as a main component and a second layer which contains titanium as a main component and which is in contact with the first layer, and is in contact with the insulating layer.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: May 9, 2017
    Assignee: Japan Display Inc.
    Inventor: Arichika Ishida
  • Patent number: 9647134
    Abstract: According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a silicon dioxide film formed on the oxide semiconductor layer and by the CVD method with a silane-based source gas, a second gate insulator film of a silicon dioxide film formed on the first gate insulator film by the CVD method with a TEOS source gas, and a gate electrode formed on the second gate insulator film.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 9, 2017
    Assignee: JAPAN DISPLAY INC.
    Inventors: Masato Hiramatsu, Masayoshi Fuchi, Arichika Ishida
  • Patent number: 9618813
    Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: April 11, 2017
    Assignee: Japan Display Inc.
    Inventors: Yohei Yamaguchi, Arichika Ishida, Hidekazu Miyake, Hiroto Miyake, Isao Suzumura
  • Patent number: 9613860
    Abstract: According to one embodiment, a method of manufacturing a thin-film transistor includes forming a semiconductor layer on a gate electrode with an insulating layer 12 being interposed, forming interconnect formation layers on the semiconductor layer, forming a plurality of interconnects and electrodes by patterning the interconnect formation layers through etching, patterning the semiconductor layer in an island shape through etching after forming the electrodes, exposing a channel region of the semiconductor layer by etching a part of the electrodes on the semiconductor layer, and forming a protective layer so as to overlap the interconnects, the electrodes and the semiconductor layer having the island shape.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: April 4, 2017
    Assignee: Japan Display Inc.
    Inventors: Isao Suzumura, Arichika Ishida, Hidekazu Miyake, Hiroto Miyake, Yohei Yamaguchi
  • Publication number: 20160268417
    Abstract: According to one embodiment, a thin-film transistor includes a semiconductor layer SC including a channel region, and a source region and a drain region on both sides of the channel region, a gate electrode GE, a first electrode SE connected to the source region via a first contact hole CH1, a second electrode DE connected to the drain region via a second contact hole CH2, a source line connected to the first electrode, and a drain line connected to the second electrode. A distance from the first and second contact holes to an end of the respective regions in a direction of a channel width is greater than or equal to 5 ?m and less than or equal to 30 ?m. The source line and the drain line extend in directions different from each other.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 15, 2016
    Applicant: Japan Display Inc.
    Inventors: Hidekazu MIYAKE, Arichika Ishida, Hiroto Miyake, Isao Suzumura, Yohei Yamaguchi
  • Patent number: 9412334
    Abstract: According to one embodiment, a liquid crystal display device includes an array substrate including a first color filter configured to transmit light in a first wavelength range, a second color filter configured to transmit light in a second wavelength range of greater wavelengths than the first wavelength range, a first switching element disposed above the second color filter, a second switching element disposed above the second color filter, a first pixel electrode which is electrically connected to the first switching element and is located above the first color filter, and a second pixel electrode which is electrically connected to the second switching element and is located above the second color filter.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: August 9, 2016
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hajime Watakabe, Arichika Ishida, Masato Hiramatsu
  • Publication number: 20160209719
    Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 21, 2016
    Applicant: Japan Display Inc.
    Inventors: Yohei YAMAGUCHI, Arichika ISHIDA, Hidekazu MIYAKE, Hiroto MIYAKE, lsao SUZUMURA
  • Publication number: 20160211177
    Abstract: According to one embodiment, a method of manufacturing a thin-film transistor includes forming a semiconductor layer on a gate electrode with an insulating layer 12 being interposed, forming interconnect formation layers on the semiconductor layer, forming a plurality of interconnects and electrodes by patterning the interconnect formation layers through etching, patterning the semiconductor layer in an island shape through etching after forming the electrodes, exposing a channel region of the semiconductor layer by etching a part of the electrodes on the semiconductor layer, and forming a protective layer so as to overlap the interconnects, the electrodes and the semiconductor layer having the island shape.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 21, 2016
    Applicant: Japan Display Inc.
    Inventors: lsao SUZUMURA, Arichika ISHIDA, Hidekazu MIYAKE, Hiroto MIYAKE, Yohei YAMAGUCHI
  • Publication number: 20160172503
    Abstract: According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a silicon dioxide film formed on the oxide semiconductor layer and by the CVD method with a silane-based source gas, a second gate insulator film of a silicon dioxide film formed on the first gate insulator film by the CVD method with a TEOS source gas, and a gate electrode formed on the second gate insulator film.
    Type: Application
    Filed: February 24, 2016
    Publication date: June 16, 2016
    Applicant: Japan Display Inc.
    Inventors: Masato HIRAMATSU, Masayoshi FUCHI, Arichika ISHIDA