Patents by Inventor Arnaud Regnier

Arnaud Regnier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170278577
    Abstract: The non-volatile memory device comprises memory cells each comprising a selectable state transistor having a floating gate and a control gate. The state transistor is of the depletion-mode type and is advantageously configured so as to have a threshold voltage that is preferably negative when the memory cell is in a virgin state. When the memory cell is read, a read voltage of zero may then be applied to the control gate and also to the control gates of the state transistors of all the memory cells of the memory device.
    Type: Application
    Filed: November 30, 2016
    Publication date: September 28, 2017
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 9691866
    Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 27, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel, Francesco La Rosa
  • Publication number: 20170178733
    Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Inventors: Francesco LA ROSA, Stephan NIEL, Arnaud REGNIER
  • Patent number: 9666484
    Abstract: An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: May 30, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Arnaud Regnier, Stephan Niel, Francesco La Rosa
  • Patent number: 9653470
    Abstract: The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 16, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 9627068
    Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 18, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 9613709
    Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: April 4, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Publication number: 20170084749
    Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Marc MANTELLI, Stephan NIEL, Arnaud REGNIER, Francesco LA ROSA, Julien DELALLEAU
  • Publication number: 20170011804
    Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 9543311
    Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: January 10, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Marc Mantelli, Stephan Niel, Arnaud Regnier, Francesco La Rosa, Julien Delalleau
  • Publication number: 20160372561
    Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.
    Type: Application
    Filed: August 30, 2016
    Publication date: December 22, 2016
    Inventors: Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel, Francesco La Rosa
  • Publication number: 20160336070
    Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.
    Type: Application
    Filed: December 28, 2015
    Publication date: November 17, 2016
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 9484107
    Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: November 1, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Publication number: 20160308011
    Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.
    Type: Application
    Filed: June 28, 2016
    Publication date: October 20, 2016
    Inventors: Francesco LA ROSA, Stephan NIEL, Julien DELALLEAU, Arnaud REGNIER
  • Patent number: 9461129
    Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: October 4, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel, Francesco La Rosa
  • Patent number: 9443598
    Abstract: The present disclosure relates to a method for controlling two twin memory cells each comprising a floating-gate transistor comprising a state control gate, in series with a select transistor comprising a select control gate common to the two memory cells, the drains of the floating-gate transistors being connected to a same bit line, the method comprising steps of programming the first memory cell by hot-electron injection, by applying a positive voltage to the bit line and a positive voltage to the state control gate of the first memory cell, and simultaneously, of applying to the state control gate of the second memory cell a positive voltage capable of causing a programming current to pass through the second memory cell, without switching it to a programmed state.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: September 13, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Patent number: 9406686
    Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: August 2, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Julien Delalleau, Arnaud Regnier
  • Publication number: 20160181265
    Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.
    Type: Application
    Filed: September 15, 2015
    Publication date: June 23, 2016
    Inventors: Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel, Francesco La Rosa
  • Patent number: 9368215
    Abstract: A method controls a memory that includes twin memory cells formed in a semiconductor substrate. Each memory cell includes a floating-gate transistor including a state control gate, in series with a select transistor that includes a vertical select control gate, common to the twin memory cells, and a source connected to an embedded source line, common to the memory cells. The drains of the floating-gate transistors of the twin memory cells are connected to a same bit line. The method includes controlling a memory cell so as to turn it on to couple the source line to a bit line coupled to the ground, during a step of programming or reading another memory cell.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: June 14, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Publication number: 20160071598
    Abstract: A method controls a memory that includes twin memory cells formed in a semiconductor substrate. Each memory cell includes a floating-gate transistor including a state control gate, in series with a select transistor that includes a vertical select control gate, common to the twin memory cells, and a source connected to an embedded source line, common to the memory cells. The drains of the floating-gate transistors of the twin memory cells are connected to a same bit line. The method includes controlling a memory cell so as to turn it on to couple the source line to a bit line coupled to the ground, during a step of programming or reading another memory cell.
    Type: Application
    Filed: July 27, 2015
    Publication date: March 10, 2016
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier