Patents by Inventor Arnaud Regnier

Arnaud Regnier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7242621
    Abstract: The present invention relates to a floating-gate MOS transistor, comprising drain and source regions implanted into a silicon substrate, a channel extending between the drain and source regions, a tunnel oxide, a floating gate, a gate oxide and a control gate extending according to a determined gate length. According to the present invention, the control gate comprises a small gate and a large gate arranged side by side and separated by an electrically insulating material. Application to the production of memory cells without access transistor, and to the implementation of an erase-program method with reduced electrical stress for the tunnel oxide.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: July 10, 2007
    Assignees: STMicroelectronics Rousset SAS, Universite d'Aix Marseille I
    Inventors: Jean-Michel Mirabel, Arnaud Regnier, Rachid Bouchakour, Romain Laffont, Pascal Masson
  • Publication number: 20070069278
    Abstract: A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.
    Type: Application
    Filed: September 22, 2006
    Publication date: March 29, 2007
    Applicants: STMicroelectronics S.A., STMicroelectronics (Rousset) SAS, FRANCE UNIVERSITE D'AIX-MARSEILLE I
    Inventors: Rachid Bouchakour, Virginie Bidal, Philippe Candelier, Richard Fournel, Philippe Gendrier, Romain Laffont, Pascal Masson, Jean-Michel Mirabel, Arnaud Regnier
  • Publication number: 20050286303
    Abstract: The present invention relates to a floating-gate MOS transistor, comprising drain and source regions implanted into a silicon substrate, a channel extending between the drain and source regions, a tunnel oxide, a floating gate, a gate oxide and a control gate extending according to a determined gate length. According to the present invention, the control gate comprises a small gate and a large gate arranged side by side and separated by an electrically insulating material. Application to the production of memory cells without access transistor, and to the implementation of an erase-program method with reduced electrical stress for the tunnel oxide.
    Type: Application
    Filed: June 17, 2005
    Publication date: December 29, 2005
    Applicants: STMicroelectronics Rousset SAS, Universite d'Aix Marseille I
    Inventors: Jean-Michel Mirabel, Arnaud Regnier, Rachid Bouchakour, Romain Laffont, Pascal Masson