Patents by Inventor Arun Virupaksha Gowda
Arun Virupaksha Gowda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150348952Abstract: An electronic packaging assembly having a semiconductor integrated circuit and a plurality of interconnect components is provided. The plurality of interconnect components is operatively coupled to the semiconductor integrated circuit. Further, one or more interconnect components include one or more support elements having a first surface and a second surface, and one or more spring elements having a first end and a second end, and wherein first ends of the one or more spring elements are coupled to the first surface or the second surface of a respective support element.Type: ApplicationFiled: May 27, 2014Publication date: December 3, 2015Applicant: General Electric CompanyInventors: Gamal Refai-Ahmed, David Mulford Shaddock, Arun Virupaksha Gowda, John Anthony Vogel, Christian Giovanniello
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Patent number: 9184124Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.Type: GrantFiled: November 19, 2014Date of Patent: November 10, 2015Assignee: General Electric CompanyInventors: Shakti Singh Chauhan, Arun Virupaksha Gowda, Paul Alan McConnelee
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Patent number: 9171785Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.Type: GrantFiled: January 28, 2014Date of Patent: October 27, 2015Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee
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Patent number: 9165864Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.Type: GrantFiled: January 28, 2014Date of Patent: October 20, 2015Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee
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Publication number: 20150287699Abstract: A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.Type: ApplicationFiled: June 18, 2015Publication date: October 8, 2015Inventors: Paul Alan McConnelee, Arun Virupaksha Gowda
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Publication number: 20150255418Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.Type: ApplicationFiled: March 4, 2014Publication date: September 10, 2015Applicant: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
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Patent number: 9117813Abstract: A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.Type: GrantFiled: June 15, 2012Date of Patent: August 25, 2015Assignee: General Electric CompanyInventors: Paul Alan McConnelee, Arun Virupaksha Gowda
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Publication number: 20150194375Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.Type: ApplicationFiled: March 23, 2015Publication date: July 9, 2015Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
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Patent number: 9066443Abstract: A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.Type: GrantFiled: September 13, 2011Date of Patent: June 23, 2015Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Donald Paul Cunningham, Shakti Singh Chauhan
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Publication number: 20150171036Abstract: A chip package includes a first substrate having at least one circuit layer formed on a first surface thereof, a first die mounted on a second surface of the first substrate opposite from the first surface, and an interconnection assembly comprising upper and lower conductive layers provided on an insulating substrate, with the upper conductive layer of the interconnection assembly affixed to the second surface of the first substrate and electrically connected to the at least one circuit layer of the first substrate. A second substrate is positioned on a side of the first die opposite from the first substrate so as to position the die between the first and second substrates, the second substrate having at least one circuit layer formed on an outward facing first surface thereof that is electrically connected to at least one of the lower conductive layers of the interconnection assembly and the first die.Type: ApplicationFiled: February 19, 2015Publication date: June 18, 2015Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Kevin Matthew Durocher, Scott Smith, Donald Paul Cunningham
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Publication number: 20150108513Abstract: A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.Type: ApplicationFiled: December 22, 2014Publication date: April 23, 2015Inventors: Arun Virupaksha Gowda, Donald Paul Cunningham, Shakti Singh Chauhan
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Publication number: 20150084207Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Applicant: General Electric CompanyInventors: Shakti Singh Chauhan, Paul Alan McConnelee, Arun Virupaksha Gowda
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Patent number: 8987876Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.Type: GrantFiled: May 20, 2013Date of Patent: March 24, 2015Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
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Publication number: 20150069612Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.Type: ApplicationFiled: November 19, 2014Publication date: March 12, 2015Inventors: Shakti Singh Chauhan, Arun Virupaksha Gowda, Paul Alan McConnelee
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Patent number: 8941208Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.Type: GrantFiled: July 30, 2012Date of Patent: January 27, 2015Assignee: General Electric CompanyInventors: Shakti Singh Chauhan, Arun Virupaksha Gowda, Paul Alan McConnelee
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Patent number: 8916996Abstract: An apparatus, such as an electrical distribution system, is provided. The apparatus can include a first conductor and a second conductor. Multiple conduction paths can form parallel electrical connections along a connection span between the first and second conductors, with each of the conduction paths having a respectively similar nominal electrical resistance. The first and second conductors can have respective cross-sectional areas that decrease in opposing directions along said connection span.Type: GrantFiled: July 29, 2011Date of Patent: December 23, 2014Assignee: General Electric CompanyInventors: Marco Francesco Aimi, Arun Virupaksha Gowda, Jianjun Jiang
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Patent number: 8853550Abstract: A circuit board includes a solder wettable surface and a metal mask configured to restrict solder from flowing outside the solder wettable surface of the circuit board.Type: GrantFiled: February 25, 2011Date of Patent: October 7, 2014Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Kevin Matthew Durocher, James Wilson Rose, Paul Jeffrey Gillespie, Richard Alfred Beaupre, David Richard Esler
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Publication number: 20140264800Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.Type: ApplicationFiled: May 20, 2013Publication date: September 18, 2014Applicant: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
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Publication number: 20140264799Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.Type: ApplicationFiled: May 20, 2013Publication date: September 18, 2014Applicant: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
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Patent number: 8742558Abstract: A method of protecting sensitive components prior to, during or subsequent to advanced die packaging processing includes applying a metal stack layer such as titanium/copper (Ti/Cu) onto the front surface of a die assembly such that the die assembly front surface is covered with the metal stack layer. A layer of titanium/copper/titanium (Ti/Cu/Ti) or a solder alloy is also applied to the back surface of the die assembly such that the back surface of the die assembly is covered with the Ti/Cu/Ti layer or solder alloy. The front surface metal stack layer and the back surface Ti/Cu/Ti layer or solder alloy prevent degradation of die metallization prior to, during or subsequent to the advanced die packaging processing.Type: GrantFiled: May 21, 2008Date of Patent: June 3, 2014Assignee: General Electric CompanyInventors: Paul Alan McConnelee, Arun Virupaksha Gowda, Elizabeth Ann Burke, Kevin Matthew Durocher