Patents by Inventor Arun Virupaksha Gowda
Arun Virupaksha Gowda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140138806Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.Type: ApplicationFiled: January 28, 2014Publication date: May 22, 2014Applicant: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee
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Publication number: 20140138807Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.Type: ApplicationFiled: January 28, 2014Publication date: May 22, 2014Applicant: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee
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Patent number: 8716870Abstract: A semiconductor device package having direct write interconnections and method of manufacturing thereof is disclosed. A device package is formed by providing a substrate structure, attaching at least one device to the substrate structure that each include a substrate and one or more connection pads formed on the substrate, depositing a dielectric layer over the at least one device and onto the substrate structure by way of a direct write application, the dielectric layer including vias formed therethrough, and forming an interconnect structure on the dielectric layer that is electrically coupled to the connection pads of the at least one device, the interconnect structure extending through the vias in the dielectric layer so as to be connected to the connection pads.Type: GrantFiled: December 16, 2011Date of Patent: May 6, 2014Assignee: General Electric CompanyInventor: Arun Virupaksha Gowda
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Patent number: 8653635Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.Type: GrantFiled: August 16, 2011Date of Patent: February 18, 2014Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Paul Alan McConnelee
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Publication number: 20140029234Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Inventors: Shakti Singh Chauhan, Arun Virupaksha Gowda, Paul Alan McConnelee
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Publication number: 20140029210Abstract: A surface-mount package structure for reducing the ingress of moisture and gases thereto is disclosed. The surface-mount structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to a substrate structure, with a dielectric material positioned between the dielectric layer and the substrate structure to fill in gaps in the surface-mount structure.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Ri-an Zhao, Shakti Singh Chauhan
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Publication number: 20130334706Abstract: A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.Type: ApplicationFiled: June 15, 2012Publication date: December 19, 2013Inventors: Paul Alan McConnelee, Arun Virupaksha Gowda
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Patent number: 8586421Abstract: A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.Type: GrantFiled: September 7, 2012Date of Patent: November 19, 2013Assignee: General Electric CompanyInventors: Richard Alfred Beaupre, Paul Alan McConnelee, Arun Virupaksha Gowda, Thomas Bert Gorczyca
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Patent number: 8531027Abstract: Systems and methods for utilizing power overlay (POL) technology and semiconductor press-pack technology to produce semiconductor packages with higher reliability and power density are provided. A POL structure may interconnect semiconductor devices within a semiconductor package, and certain embodiments may be implemented to reduce the probability of damaging the semiconductor devices during the pressing of the conductive plates. In one embodiment, springs and/or spacers may be used to reduce or control the force applied by an emitter plate onto the semiconductor devices in the package. In another embodiment, the emitter plate may be recessed to exert force on the POL structure, rather than directly against the semiconductor devices. Further, in some embodiments, the conductive layer of the POL structure may be grown to function as an emitter plate, and regions of the conductive layer may be made porous to provide compliance.Type: GrantFiled: April 30, 2010Date of Patent: September 10, 2013Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Ahmed Elasser, Satish Sivarama Gunturi
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Patent number: 8487416Abstract: A power module includes at least one semiconductor die holding structure. Each die holding structure has a substantially cylindrical outer profile and a central axis. Each die holding structure is disposed within a common cylindrical EMI shield. A plurality of semiconductor devices are mounted to each die holding structure to form a substantially symmetric die mounting pattern respect to the central axis of the die holding structure.Type: GrantFiled: September 28, 2011Date of Patent: July 16, 2013Assignee: General Electric CompanyInventors: Eladio Clemente Delgado, Arun Virupaksha Gowda, Antonio Caiafa, Brian Lynn Rowden, Ljubisa Dragoljub Stevanovic, Richard Alfred Beaupre
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Publication number: 20130154110Abstract: A semiconductor device package having direct write interconnections and method of manufacturing thereof is disclosed. A device package is formed by providing a substrate structure, attaching at least one device to the substrate structure that each include a substrate and one or more connection pads formed on the substrate, depositing a dielectric layer over the at least one device and onto the substrate structure by way of a direct write application, the dielectric layer including vias formed therethrough, and forming an interconnect structure on the dielectric layer that is electrically coupled to the connection pads of the at least one device, the interconnect structure extending through the vias in the dielectric layer so as to be connected to the connection pads.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Inventor: Arun Virupaksha Gowda
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Publication number: 20130075878Abstract: A power module includes at least one semiconductor die holding structure. Each die holding structure has a substantially cylindrical outer profile and a central axis. Each die holding structure is disposed within a common cylindrical EMI shield. A plurality of semiconductor devices are mounted to each die holding structure to form a substantially symmetric die mounting pattern respect to the central axis of the die holding structure.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Applicant: GENERAL ELECTRIC COMPANYInventors: Eladio Clemente Delgado, Arun Virupaksha Gowda, Antonio Caiafa, Brian Lynn Rowden, Ljubisa Dragoljub Stevanovic, Richard Alfred Beaupre
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Publication number: 20130062630Abstract: A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Inventors: Arun Virupaksha Gowda, Donald Paul Cunningham, Shakti Singh Chauhan
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Publication number: 20130043571Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.Type: ApplicationFiled: August 16, 2011Publication date: February 21, 2013Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee
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Publication number: 20130025934Abstract: An apparatus, such as an electrical distribution system, is provided. The apparatus can include a first conductor and a second conductor. Multiple conduction paths can form parallel electrical connections along a connection span between the first and second conductors, with each of the conduction paths having a respectively similar nominal electrical resistance. The first and second conductors can have respective cross-sectional areas that decrease in opposing directions along said connection span.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: GENERAL ELECTRIC COMPANYInventors: Marco Francesco Aimi, Arun Virupaksha Gowda, Jianjun Jiang
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Patent number: 8358000Abstract: A power module includes one or more semiconductor power devices having a power overlay (POL) bonded thereto. A first heat sink is bonded to the semiconductor power devices on a side opposite the POL. A second heat sink is bonded to the POL opposite the side of the POL bonded to the semiconductor power devices. The semiconductor power devices, POL, first channel heat sink, and second channel heat sink together form a double side cooled power overlay module. The second channel heat sink is bonded to the POL solely via a compliant thermal interface material without the need for planarizing, brazing or metallurgical bonding.Type: GrantFiled: March 13, 2009Date of Patent: January 22, 2013Assignee: General Electric CompanyInventors: Richard Alfred Beaupre, Arun Virupaksha Gowda, Ljubisa Dragol jub Stevanovic, Stephen Adam Solovitz
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Publication number: 20120329207Abstract: A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.Type: ApplicationFiled: September 7, 2012Publication date: December 27, 2012Inventors: Richard Alfred Beaupre, Paul Alan McConnelee, Arun Virupaksha Gowda, Thomas Bert Gorczyca
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Patent number: 8334593Abstract: A semiconductor device package is provided. The semiconductor device package includes a laminate comprising a first metal layer disposed on a dielectric film; a plurality of vias extending through the laminate according to a predetermined pattern; one or more semiconductor devices attached to the dielectric film such that the semiconductor device contacts one or more vias; a patterned interconnect layer disposed on dielectric film, said patterned interconnect layer comprising one or more patterned regions of the first metal layer and an electrically conductive layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor device. The patterned interconnect layer comprises a top interconnect region and a via interconnect region, wherein the package interconnect region has a thickness greater than a thickness of the via interconnect region.Type: GrantFiled: January 13, 2012Date of Patent: December 18, 2012Assignee: General Electric CompanyInventors: Paul Alan McConnelee, Arun Virupaksha Gowda
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Patent number: 8310040Abstract: A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.Type: GrantFiled: December 8, 2010Date of Patent: November 13, 2012Assignee: General Electric CompanyInventors: Richard Alfred Beaupre, Paul Alan McConnelee, Arun Virupaksha Gowda, Thomas Bert Gorczyca
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Publication number: 20120161325Abstract: A semiconductor device package is provided. The semiconductor device package includes a laminate comprising a first metal layer disposed on a dielectric film; a plurality of vias extending through the laminate according to a predetermined pattern; one or more semiconductor devices attached to the dielectric film such that the semiconductor device contacts one or more vias; a patterned interconnect layer disposed on dielectric film, said patterned interconnect layer comprising one or more patterned regions of the first metal layer and an electrically conductive layer, wherein a portion of the patterned interconnect layer extends through one or more vias to form an electrical contact with the semiconductor device. The patterned interconnect layer comprises a top interconnect region and a via interconnect region, wherein the package interconnect region has a thickness greater than a thickness of the via interconnect region.Type: ApplicationFiled: January 13, 2012Publication date: June 28, 2012Applicant: GENERAL ELECTRIC COMPANYInventors: Paul Alan McConnelee, Arun Virupaksha Gowda