Patents by Inventor Arvind

Arvind has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5560029
    Abstract: A multiprocessor system comprises a plurality of processing nodes, each node processing multiple threads of computation. Each node includes a data processor which sequentially processes blocks of code, each block defining a thread of computation. The code includes instructions to send start messages with data values to start new threads of computation. Each node also includes a synchronization coprocessor for processing start messages from the same and other nodes of the system. The coprocessor processes the messages from a message queue to store values as operands for threads of computation, to determine when all operands required for a thread of computation have been received and to provide in a continuation queue an indication to the data processor that a thread of computation may be initiated. The data processor subsequently nonsynchronously initiates the thread of computation. Alternatively, a single processor may perform the continuation and message processing functions in an interleaved sequence.
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: September 24, 1996
    Assignee: Massachusetts Institute of Technology
    Inventors: Gregory M. Papadopoulos, Rishiyur S. Nikhil, Robert J. Greiner, Arvind
  • Patent number: 5499349
    Abstract: A multithreaded parallel data processing system has at least one processing element for processing multiple threads of computation. Threads are described by thread descriptors or tokens which are stored while waiting to be processed in a thread descriptor storage. Thread descriptors are comprised of an instruction pointer and a frame pointer. The instruction pointer points to the next instruction to be executed, and the frame pointer points to a frame of memory locations that the next instruction will operate on. Included within the instruction set of the at least one processing element is a fork instruction generates two thread descriptors which are added to the current thread descriptors, a start instruction on a first processor sends a message containing a thread descriptor to a second processor, and a join instruction joins two threads by producing a single thread descriptor when both of the joining threads have reached a join instruction.
    Type: Grant
    Filed: October 3, 1994
    Date of Patent: March 12, 1996
    Assignee: Massachusetts Institute of Technology
    Inventors: Rishiyur S. Nikhil, Arvind
  • Patent number: 5430850
    Abstract: A multiprocessor system comprises a plurality of processing nodes, each node processing multiple threads of computation. Each node includes a data processor which sequentially processes blocks of code, each block defining a thread of computation. The code includes instructions to send start messages with data values to start new threads of computation. Each node also includes a synchronization coprocessor for processing start messages from the same and other nodes of the system. The coprocessor processes the start messages to store values as operands for threads of computation, to determine when all operands required for a thread of computation have been received and to provide an indication to the data processor that a thread of computation may be initiated. The data processor subsequently nonsynchronously initiates the thread of computation. Preferably, the processors load and store from and to a common memory with the translation from a local virtual address to a local physical address.
    Type: Grant
    Filed: July 22, 1991
    Date of Patent: July 4, 1995
    Assignee: Massachusetts Institute of Technology
    Inventors: Gregory M. Papadopoulos, Rishiyur S. Nikhil, Robert J. Greiner, Arvind
  • Patent number: 5353418
    Abstract: A multithreaded parallel data processing system has at least one processing element for processing multiple threads of computation. Threads are described by thread descriptors which are stored while waiting to be processed in a thread descriptor storage. Thread descriptors are comprised of an instruction pointer and a frame pointer. The instruction pointer points to the next instruction to be executed, and the frame pointer points to a frame of memory locations that the next instruction will operate on. Included within the instruction on set of the at least one processing element is a load instruction that loads global data into local processing element memory that is performed to two phases: a request phase and a response phase. Also included are instructions to fork a thread into two threads and to join two threads into a single thread.
    Type: Grant
    Filed: May 21, 1990
    Date of Patent: October 4, 1994
    Assignee: Massachusetts Institute of Technology
    Inventors: Rishiyur S. Nikhil, Arvind
  • Patent number: 5241635
    Abstract: A data flow processing system has a plurality of processing elements and memory units. Communication amongst processing elements and amongst processing elements and memory units is facilitated by an interconnection network. Each processing element is pipelined. The system operates upon data objects known as tokens. The tokens initiate activity within the processing element pipelines. Included within the activities initiated by the tokens is execution of instructions. Operands for instructions are matched in non-associative portions of memory known as activation frames. The activation frame memory locations have a state field that indicates whether a value is present or not in the activation frame. The state field may also indicate other information about an activation frame memory location. The state field is used to determine what action is taken at an activation frame memory location when an instruction is executed. The state field also determines the scheduling of execution of instructions.
    Type: Grant
    Filed: August 21, 1989
    Date of Patent: August 31, 1993
    Assignee: Massachusetts Institute of Technology
    Inventors: Gregory M. Papadopoulos, David E. Culler, Arvind