Patents by Inventor Arvind

Arvind has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12346966
    Abstract: Aspects of the disclosure relate to a dual-system reconciliation process of trades. A first real-time trade processing and centralized reconciliation engine may continuously process trades in real-time and may perform centralized reconciliation of the trades. An anomaly detection and reconciliation mesh analysis engine may tokenize trade metadata received from the first real-time trade processing and centralized reconciliation engine, generate tokenized trade digital DNA, generate hashed tokenized trade digital DNA, evaluate and validate the hashed data, and perform decentralized reconciliation mesh analysis of the hashed data using a reconciliation mesh. The anomaly detection and reconciliation mesh analysis engine may send one or more monitory policies from the reconciliation mesh to a user device and may receive a first monitory policy selection from the user device.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: July 1, 2025
    Assignee: Bank of America Corporation
    Inventors: Sakshi Bakshi, Sharat Chandran, Arif Ahmad Khan, Durga Prasad Kutthumolu, Kapil Juneja, Arvind Bansal
  • Publication number: 20250206822
    Abstract: The present application relates to antibodies specifically binding to the V-domain immunoglobulin-containing suppressor of T-cell activation (VISTA) at acidic pH and their use in cancer treatment. In some embodiments, the antibodies bind specifically to human VISTA at acidic pH, but do not significantly bind to human VISTA at neutral or physiological pH.
    Type: Application
    Filed: November 25, 2024
    Publication date: June 26, 2025
    Applicants: Five Prime Therapeutics, Inc., Bristol-Myers Squibb Company
    Inventors: Robert J. Johnston, Arvind Rajpal, Paul O. Sheppard, Luis Borges, Andrew Rankin, Keith Sadoon Bahjat, Alan J. Korman, Andy X. Deng, Lin Hui Su, Ginger Rakestraw
  • Publication number: 20250212009
    Abstract: Communication management hardware receives input indicating an alternative site in which to install a first wireless access point. The alternative site is different than an original site selected for installation of the first wireless access point. The communication management hardware predicts a wireless coverage associated with installation of the first wireless access point at the alternative site. Based on the predicted wireless coverage, assigning a performance metric to the installation of the first wireless access point at the alternative site. The communication management hardware can be configured to wirelessly transmit the performance metric to an installation technician for review. The installation technician may select the alternative site based upon the performance metric.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Inventors: Pareshkumar Panchal, Muhib Taiye Oduwaiye, Clyde A. Chappell, Arvind Kopparapu, Noah Y. Polizzotto
  • Publication number: 20250211085
    Abstract: Embodiments herein relate to a switched capacitor power converter which reduces the leakage current through a power switch when the power switch is turned off. In one aspect, a first charge pump provides a voltage Vcc_cp which is higher than a power supply voltage Vcc, and a second charge pump provides a voltage Vss_cp which is lower than a ground voltage Vss. Transistors are used to couple the first charge pump to the control gate of a p-type power switch and to couple the second charge pump to the control gate of an n-type power switch. In another example implementation, the voltage of the power switch is pulled up or down using a bootstrap capacitor.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Inventors: Huanhuan Zhang, Arvind Raghavan, Christopher Schaef, Keng Chen, Sivaraman Masilamani, Yura Kocharyan
  • Publication number: 20250205352
    Abstract: The present disclosure is related to oligonucleotides, antibody-siRNA conjugates, or pharmaceutical compositions thereof for inhibiting the expression of Nav1.8 gene and methods of using such oligonucleotides, antibody-siRNA conjugates, or pharmaceutical compositions thereof in reducing/treating pain or diseases/disorders related to Nav1.8.
    Type: Application
    Filed: December 10, 2024
    Publication date: June 26, 2025
    Inventors: Jeffrey BOYLES, Arvind BHATTACHARYA, Patricia BROWN-AUGSBURGER, Michael Caramian COCHRAN, Julian DAVIES, Wendy Loza HOBBS, Yu Yan KWAN, Jonatan MATALONGA BORREL, Jeff S. McDERMOTT, Thiago OLIVA DETANICO, Christopher Earle WALL
  • Publication number: 20250211302
    Abstract: Disclosed herein are devices, methods, and systems for predicting channel status information (CSI) values and their confidence levels. The system may obtain a current CSI value of a wireless channel at a current time and generate, based on the current CSI value and a learning model that is based on CSI values and CSI predictions, a predicted CSI value and a confidence metric. The system may generate a recommended periodicity of CSI measurements of the wireless channel. In addition, the confidence metric is for the predicted CSI value based on the learning model, wherein the confidence metric indicates a level of confidence in the predicted CSI value for the prediction time. The system may adjust a scheduling parameter for the wireless channel based on the predicted CSI value and the confidence metric.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Inventors: Arvind MERWADAY, Rath VANNITHAMBY
  • Patent number: 12340190
    Abstract: According to a computing method a compiler determines a recompute node included in a dataflow application and a checkpoint tensor produced by the recompute node. The compiler determines a recompute cost to recompute the checkpoint tensor, and a memory cost to checkpoint the checkpoint tensor in a memory. Based on the recompute cost and/or the memory cost, the compiler determines a solution cost and compares the solution cost to a solution threshold. Based on comparing the solution cost to the solution threshold, the compiler determines a checkpoint solution to execute the dataflow application. The checkpoint solution can comprise recomputing or checkpointing the checkpoint tensor. In some implementations, the compiler can determine a recompute ratio of the recompute cost to the memory cost and can compare the recompute ratio to the solution threshold. A computer program product and a computing system can implement aspects of the method.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: June 24, 2025
    Assignee: SambaNova Systems, Inc.
    Inventors: Bowen Yang, Zhuo Chen, Fei Wang, Venkat Krishna Srinivasan, Chen Liu, Junjue Wang, Arvind Krishna Sujeeth, Sumti Jairath
  • Publication number: 20250197794
    Abstract: The present invention provides a membrane rupture solution comprising: one or more purified non-ionic detergents, wherein at least one of the detergents has a surface activity property that is suitable for viral vector/protein stabilization against shear stress, and, optionally, a scavenger.
    Type: Application
    Filed: October 14, 2021
    Publication date: June 19, 2025
    Applicant: Avantor Performance Materials, LLC
    Inventors: Arvind Srivastava, Nandkumar Deorkar, Lori Fortin, Jungmin Oh, Courtney O'Dell, Pranav S. Vengsarkar
  • Publication number: 20250196123
    Abstract: In one aspect, a composition is provided, comprising an ion exchange resin and a binder. In some embodiments, the ion exchange resin may be a synthetic zeolite. A water softener is also provided, comprising a composition comprising an ion exchange resin and a binder. A method for producing the composition is also provided, comprising providing an ion exchange resin and a binder, combining the ion exchange resin and the binder so as to form a homogeneous mixture, combining the homogeneous mixture with water so as to form a wetted mixture, and subjecting the wetted mixture to agglomeration.
    Type: Application
    Filed: December 19, 2024
    Publication date: June 19, 2025
    Inventors: Arvind S. Patil, Glenn F. Cueman, Selena Rhodes
  • Publication number: 20250201866
    Abstract: A bipolar plate alignment system includes a bipolar plate, a gasket seal, and an adhesive film. The bipolar plate is formed to include a seal groove and a plate alignment feature extending outwardly from a perimeter of the bipolar plate. The gasket seal is sized to fit within the seal groove and is formed to include a seal alignment feature extending outwardly from a perimeter of the gasket seal.
    Type: Application
    Filed: December 10, 2024
    Publication date: June 19, 2025
    Inventors: Yunsheng JIANG, Udit N. SHRIVASTAVA, Anson SINANAN, Antimo GRAZIANO, Akhil SHRIVASTAVA, Naveen THIRUNAVUKKARASU, Barathram JAYASANKAR, Arvind V. HARINATH
  • Publication number: 20250199899
    Abstract: In one embodiment, an apparatus includes: first and second cores to execute instructions, and an interface circuit coupled to the first and second cores. In a lockstep mode in which the first and second cores are to execute redundantly, the interface circuit is to identify a miscompare between the first core and the second core that is due to a corrected error in one of the first core or the second core, and indicate the miscompare as a recoverable error. Other embodiments are described and claimed.
    Type: Application
    Filed: December 18, 2023
    Publication date: June 19, 2025
    Inventors: Samuel Mattord, Arvind Raman
  • Publication number: 20250199702
    Abstract: A storage device may reduce increases to a program erase cycle count associated with a physical block by forming super blocks of varying sizes. A memory device on the storage device includes one or more dies, each of which is divided into physical blocks. A controller may identify characteristics of data to be stored on the memory device. The controller may then select physical blocks from the one or more dies to be used in forming a super block and optimize the super block configuration based on data characteristics. In forming the super block with one or more physical blocks, the controller may align the super block size with the data characteristics. By aligning the super block size with the data characteristics, data relocation on the super block may be reduced and increases to the program erase cycle count associated with a physical block may be reduced.
    Type: Application
    Filed: December 15, 2023
    Publication date: June 19, 2025
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dhanunjaya Rao Gorrle, Leeladhar Agarwal, Arvind Bhushan
  • Publication number: 20250199089
    Abstract: In some embodiments, the disclosure is directed to a system for estimating high-side voltage of transformers in an electrical distribution network. In some embodiments, the system executes program instructions that enable one or more computers to receive meter load and/or voltage data from smart meters. In some embodiments, the data is used in transformer load analysis to assume impedance values, determining low-side voltage, and estimating high-side voltage using the determined low-side voltage. In some embodiments, the system is configured to these estimations against known values to identify discrepancies, which are output via a graphical user interface. In some embodiments, the system is configured to determine expected percent impedance from historical data and/or estimate impedance characteristics. In some embodiments, the system is configured to execute clustering of voltage estimates to identify similar phases among neighboring transformers.
    Type: Application
    Filed: December 16, 2024
    Publication date: June 19, 2025
    Inventors: Devon Yates, Arvind Simhadri, Jacinto Chen, Ryan Scarbrough
  • Patent number: 12332836
    Abstract: A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for determining scaled logical edge bandwidths in an operation unit graph in preparation of placing and routing the operation unit graph onto a reconfigurable processor. The cost estimation tool may be configured to receive the operation unit graph, divide the operation unit graph in first and second subgraphs, determine maximum latencies of the first and second subgraphs, and determine a scaled logical edge bandwidth of a logical edge that couples a first logical unit of M logical units in the first subgraph with a second logical unit of N logical units in the first subgraph based on M, N, and scaled bandwidth limits of the M and N logical units.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: June 17, 2025
    Assignee: SambaNova Systems, Inc.
    Inventors: Yue Fu, Kin Hing Leung, Joshua Brot, Arvind Krishna Sujeeth, Sumti Jairath, Andrew Deng, Raghu Prabhakar
  • Patent number: 12331045
    Abstract: Disclosed are compounds of Formula (I): or stereoisomers, tautomers, or salts thereof, wherein each R is independently H or D. Also disclosed are methods of using such compounds to decrease the levels of IKZF1-4 proteins; and pharmaceutical compositions comprising the compound. The compounds are useful in the treatment of viral infections and proliferative disorders, such as cancer.
    Type: Grant
    Filed: December 4, 2024
    Date of Patent: June 17, 2025
    Assignee: Bristol-Myers Squibb Company
    Inventors: Lan-Ying Qin, Zheming Ruan, Ashok Vinayak Purandare, Emily Charlotte Cherney, James Aaron Balog, Arvind Mathur, Samuel J. Bonacorsi
  • Patent number: 12330313
    Abstract: A mobile robot includes: a chassis supporting a locomotive assembly; a sensor; a processor configured, in a guided travel mode, to: detect an external force applied to the chassis in a first direction; control the sensor to capture sensor data corresponding to a physical environment of the mobile robot; detect, based on the sensor data, an operational constraint in the physical environment; determine, based on the detected operational constraint, a feedback force in a second direction opposite the first direction; and controlling the locomotive assembly according to the feedback force.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: June 17, 2025
    Assignee: Zebra Technologies Corporation
    Inventors: Achal Dasa Arvind, Benjamin Narin, Melonee Wise, Derek King
  • Patent number: 12333283
    Abstract: In a method a compiler performs a trial compilation to a low level (LL) intermediate representation (IR) of a high level (HL) decision to execute a dataflow application on a computing system. The LLIR comprises hardware resources to execute the application based on the HL decision and the compiler determines a trial result based on LL execution metrics associated with the trail compilation. The compiler performs a trial compilation of a second HL decision to a second LLIR and determines a trial result based on LL execution metrics associated with the second trail compilation. The compiler evaluates the trial results and, based on the evaluations, selects one or both of the HL decisions for executing the dataflow application. A computer program product and a computing system can implement the method.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: June 17, 2025
    Assignee: SambaNova Systems, Inc.
    Inventors: Blaine Rister, Haocheng Dong, David Alan Koeplinger, Yaqi Zhang, Junjue Wang, Zhuo Chen, Arvind Sujeeth
  • Patent number: 12336012
    Abstract: Aspects described herein relate to determining whether full duplex (FD) communications are configured during resources for communicating one or more messages of a random access procedure, where the FD communications comprising uplink communications and downlink communications occurring in a same frequency band, and responsive to the determining whether the FD communications are configured during the resources, transmitting the one or more messages of the random access procedure using the resources.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: June 17, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Hung Dinh Ly, June Namgoong, Muhammad Sayed Khairy Abdelghaffar, Krishna Kiran Mukkavilli, Tingfang Ji, Huilin Xu, Shimman Arvind Patel, Wanshi Chen
  • Patent number: 12333253
    Abstract: An apparatus is disclosed which includes at least one processing device comprising a processor coupled to a memory. The at least one processing device, when executing program code, is configured to: extract one or more entities identified in a plurality of data artifacts based at least in part on one or more datasets, extract one or more entities identified in a plurality of code artifacts based at least in part on the one or more datasets, extract one or more entities identified in a plurality of user interface artifacts based at least in part on the one or more datasets, generate a set of dependency graphs each based at least in part on one or more relationships among the respective extracted one or more entities, and perform one or more of a lexical analysis and a semantic analysis on the set of dependency graphs to identify a data domain of the one or more datasets.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: June 17, 2025
    Assignee: International Business Machines Corporation
    Inventors: Malolan Chetlur, Arvind Agarwal, Subhendu Dey, Sameep Mehta, Sandipan Sarkar
  • Publication number: 20250190286
    Abstract: A method, computer program product, and computer system for processing events in an event-driven architecture. A dynamic scan of log data generated from multiple executions of a software program that executes events is performed. The dynamic scan identifies events that occurred and event triggers that invoked the identified events or invoked other event triggers. An event hierarchy that includes event nodes and events edges connects event nodes is generated by organizing the identified events and event triggers into the event hierarchy. Each event node satisfying criteria involving a frequency of occurrence of the events directly or indirectly invoked by each event node is tagged. An event message having a header portion that includes an identification of all tagged event nodes and a body portion that includes event attributes. The header portion, but not the body portion, of the event message is sent to event subscribers.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 12, 2025
    Inventors: Tanmay Arvind Ambre, Amit Deshpande, Harish Bharti, Rajesh Kumar Saxena, Balakrishnan Sreenivasan