Patents by Inventor Arvind Kamath

Arvind Kamath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8822301
    Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: September 2, 2014
    Assignee: Thin Film Electronics ASA
    Inventors: Arvind Kamath, Erik Scher, Patrick Smith, Aditi Chandra, Steven Molesa
  • Patent number: 8796774
    Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: August 5, 2014
    Assignee: Thin Film Electronics ASA
    Inventors: Arvind Kamath, Patrick Smith, James Montague Cleeves
  • Patent number: 8796125
    Abstract: A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: August 5, 2014
    Assignee: Kovio, Inc.
    Inventors: Joerg Rockenberger, James Montague Cleeves, Arvind Kamath
  • Publication number: 20140094004
    Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.
    Type: Application
    Filed: October 2, 2012
    Publication date: April 3, 2014
    Inventors: Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Patrick Smith, Fabio Zürcher
  • Publication number: 20140091909
    Abstract: The present invention relates to surveillance and/or identification devices having capacitors connected in parallel or in series, and methods of making and using such devices. Devices with capacitors connected in parallel, where one capacitor is fabricated with a relatively thick capacitor dielectric and another is fabricated with a relatively thin capacitor dielectric achieve both a high-precision capacitance and a low breakdown voltage for relatively easy surveillance tag deactivation. Devices with capacitors connected in series result in increased lateral dimensions of a small capacitor. This makes the capacitor easier to fabricate using techniques that may have relatively limited resolution capabilities.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 3, 2014
    Inventors: Patrick SMITH, Criswell CHOI, James Montague CLEEVES, Vivek SUBRAMANIAN, Arvind KAMATH, Steven MOLESA
  • Patent number: 8617992
    Abstract: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: December 31, 2013
    Assignee: Kovio, Inc.
    Inventors: Aditi Chandra, Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Mao Takashima, Erik Scher
  • Publication number: 20130344301
    Abstract: Embodiments relate to printing features from an ink containing a material precursor. In some embodiments, the material includes an electrically active material, such as a semiconductor, a metal, or a combination thereof. In another embodiment, the material includes a dielectric. The embodiments provide improved printing process conditions that allow for more precise control of the shape, profile and dimensions of a printed line or other feature. The composition(s) and/or method(s) improve control of pinning by increasing the viscosity and mass loading of components in the ink. An exemplary method thus includes printing an ink comprising a material precursor and a solvent in a pattern on the substrate; precipitating the precursor in the pattern to form a pinning line; substantially evaporating the solvent to form a feature of the material precursor defined by the pinning line; and converting the material precursor to the patterned material.
    Type: Application
    Filed: August 23, 2013
    Publication date: December 26, 2013
    Inventors: Erik SCHER, Steven MOLESA, Joerg ROCKENBERGER, Arvind KAMATH, Ikuo MORI, Wenzhuo GUO, Dmitry KARSHTEDT, Vladimir DIOUMAEV
  • Publication number: 20130243940
    Abstract: Devices on a diffusion barrier coated metal substrates, and methods of making the same are disclosed. The devices include a metal substrate, a diffusion barrier layer on the metal substrate, one or more insulator layers on the diffusion barrier layer, and an antenna and/or inductor on the one or more insulator layer(s). The method includes forming a diffusion barrier layer on the metal substrate, forming one or more insulator layers on the diffusion barrier layer; and forming an antenna and/or inductor on an uppermost one of the insulator layer(s). The antenna and/or inductor is electrically connected to at least one of the diffusion barrier layer and/or the metal substrate. Such diffusion barrier coated substrates prevent diffusion of metal atoms from the metal substrate into device layers formed thereon.
    Type: Application
    Filed: April 29, 2013
    Publication date: September 19, 2013
    Inventors: Arvind KAMATH, Michael KOCSIS, Kevin MCCARTHY, Gloria WONG, Jiang LI
  • Patent number: 8530589
    Abstract: Embodiments relate to printing features from an ink containing a material precursor. In some embodiments, the material includes an electrically active material, such as a semiconductor, a metal, or a combination thereof. In another embodiment, the material includes a dielectric. The embodiments provide improved printing process conditions that allow for more precise control of the shape, profile and dimensions of a printed line or other feature. The composition(s) and/or method(s) improve control of pinning by increasing the viscosity and mass loading of components in the ink. An exemplary method thus includes printing an ink comprising a material precursor and a solvent in a pattern on the substrate; precipitating the precursor in the pattern to form a pinning line; substantially evaporating the solvent to form a feature of the material precursor defined by the pinning line; and converting the material precursor to the patterned material.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: September 10, 2013
    Assignee: Kovio, Inc.
    Inventors: Erik Scher, Steven Molesa, Joerg Rockenberger, Arvind Kamath, Ikuo Mori
  • Publication number: 20130189823
    Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature.
    Type: Application
    Filed: March 8, 2013
    Publication date: July 25, 2013
    Inventors: Arvind KAMATH, Erik SCHER, Patrick SMITH, Aditi CHANDRA, Steven MOLESA
  • Patent number: 8460983
    Abstract: Doped semiconductor ink formulations, methods of making doped semiconductor ink formulations, methods of coating or printing thin films, methods of forming electronic devices and/or structures from the thin films, and methods for modifying and controlling the threshold voltage of a thin film transistor using the films are disclosed. A desired dopant may be added to an ink formulation comprising a Group IVA compound and a solvent, and then the ink may be printed on a substrate to form thin films and conductive structures/devices, such as thin film transistors. By adding a customized amount of the dopant to the ink prior to printing, the threshold voltage of a thin film transistor made from the doped semiconductor ink may be independently controlled upon activation of the dopant.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: June 11, 2013
    Assignee: Kovio, Inc.
    Inventors: Wenzhuo Guo, Fabio Zürcher, Arvind Kamath, Joerg Rockenberger
  • Patent number: 8446706
    Abstract: High precision capacitors and methods for forming the same utilizing a precise and highly conformal deposition process for depositing an insulating layer on substrates of various roughness and composition. The method generally comprises the steps of depositing a first insulating layer on a metal substrate by atomic layer deposition (ALD); (b) forming a first capacitor electrode on the first insulating layer; and (c) forming a second insulating layer on the first insulating layer and on or adjacent to the first capacitor electrode. Embodiments provide an improved deposition process that produces a highly conformal insulating layer on a wide range of substrates, and thereby, an improved capacitor.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: May 21, 2013
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, Criswell Choi, Patrick Smith, Erik Scher, Jiang Li
  • Patent number: 8426905
    Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: April 23, 2013
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, Erik Scher, Patrick Smith, Aditi Chandra, Steven Molesa
  • Publication number: 20130069785
    Abstract: The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.
    Type: Application
    Filed: August 20, 2012
    Publication date: March 21, 2013
    Inventors: Vivek SUBRAMANIAN, Patrick Smith, Vikram Pavate, Arvind Kamath, Criswell Choi, Aditi Chandra, James Montague Cleeves
  • Publication number: 20120307569
    Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.
    Type: Application
    Filed: August 14, 2012
    Publication date: December 6, 2012
    Inventors: Arvind KAMATH, Patrick Smith, James Montague Cleeves
  • Patent number: 8304780
    Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: November 6, 2012
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Patrick Smith, Fabio Zürcher
  • Patent number: 8296943
    Abstract: The present invention relates to surveillance and/or identification devices having capacitors connected in parallel or in series, and methods of making and using such devices. Devices with capacitors connected in parallel, where one capacitor is fabricated with a relatively thick capacitor dielectric and another is fabricated with a relatively thin capacitor dielectric achieve both a high-precision capacitance and a low breakdown voltage for relatively easy surveillance tag deactivation. Devices with capacitors connected in series result in increased lateral dimensions of a small capacitor. This makes the capacitor easier to fabricate using techniques that may have relatively limited resolution capabilities.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: October 30, 2012
    Assignee: Kovio, Inc.
    Inventors: Patrick Smith, Criswell Choi, James Montague Cleeves, Vivek Subramanian, Arvind Kamath, Steven Molesa
  • Patent number: 8264027
    Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: September 11, 2012
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, Patrick Smith, James Montague Cleeves
  • Patent number: 8264359
    Abstract: The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: September 11, 2012
    Assignee: Kovio, Inc.
    Inventors: Vivek Subramanian, Patrick Smith, Vikram Pavate, Arvind Kamath, Criswell Choi, Aditi Chandra, James Montague Cleeves
  • Patent number: 8227320
    Abstract: The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: July 24, 2012
    Assignee: Kovio, Inc.
    Inventors: Vivek Subramanian, Patrick Smith, Vikram Pavate, Arvind Kamath, Criswell Choi, Aditi Chandra, James Montague Cleeves