Patents by Inventor Arvind Kamath
Arvind Kamath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120181636Abstract: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching.Type: ApplicationFiled: March 22, 2012Publication date: July 19, 2012Inventors: Aditi Chandra, Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Mao Takashima, Erik Scher
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Patent number: 8158518Abstract: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. The method of forming contacts includes depositing an ink of a silicide-forming metal onto an exposed silicon surface, drying the ink to form a silicide-forming metal precursor, and heating the silicide-forming metal precursor and the silicon surface to form a metal silicide contact. Optionally, the metal precursor ink may be selectively deposited onto a dielectric layer adjacent to the exposed silicon surface to form a metal-containing interconnect. Furthermore, one or more bulk conductive metal(s) may be deposited on remaining metal precursor ink and/or the dielectric layer. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects.Type: GrantFiled: July 17, 2008Date of Patent: April 17, 2012Assignee: Kovio, Inc.Inventors: Aditi Chandra, Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Mao Takashima, Erik Scher
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Patent number: 8021955Abstract: Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.Type: GrantFiled: October 6, 2009Date of Patent: September 20, 2011Assignee: LSI Logic CorporationInventors: Venkatesh P. Gopinath, Arvind Kamath, Mohammad R. Mirabedini, Ming-Yi Lee
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Publication number: 20110017997Abstract: Semiconductor devices on a diffusion barrier coated metal substrates, and methods of making the same are disclosed. The semiconductor devices include a metal substrate, a diffusion barrier layer on the metal substrate, an insulator layer on the diffusion barrier layer, and a semiconductor layer on the insulator layer. The method includes forming a diffusion barrier layer on the metal substrate, forming an insulator layer on the diffusion barrier layer; and forming a semiconductor layer on the insulator layer. Such diffusion barrier coated substrates prevent diffusion of metal atoms from the metal substrate into a semiconductor device formed thereon.Type: ApplicationFiled: May 28, 2010Publication date: January 27, 2011Inventors: Arvind Kamath, Michael Kocsis, Kevin McCarthy, Gloria Man Ting Wong
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Publication number: 20100244133Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.Type: ApplicationFiled: June 9, 2010Publication date: September 30, 2010Inventors: Arvind KAMATH, James Montague Cleeves, Joerg Rockenberger, Patrick Smith, Fabio Zürcher
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Patent number: 7767520Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.Type: GrantFiled: August 3, 2007Date of Patent: August 3, 2010Assignee: Kovio, Inc.Inventors: Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Patrick Smith, Fabio Zürcher
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Publication number: 20100163962Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.Type: ApplicationFiled: March 12, 2010Publication date: July 1, 2010Inventors: Arvind Kamath, Patrick Smith, James Montague Cleeves
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Publication number: 20100148859Abstract: Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g.Type: ApplicationFiled: January 19, 2010Publication date: June 17, 2010Inventors: James Montague CLEEVES, J. Devin MacKenzie, Arvind Kamath
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Publication number: 20100123582Abstract: The present invention relates to surveillance and/or identification devices having capacitors connected in parallel or in series, and methods of making and using such devices. Devices with capacitors connected in parallel, where one capacitor is fabricated with a relatively thick capacitor dielectric and another is fabricated with a relatively thin capacitor dielectric achieve both a high-precision capacitance and a low breakdown voltage for relatively easy surveillance tag deactivation. Devices with capacitors connected in series result in increased lateral dimensions of a small capacitor. This makes the capacitor easier to fabricate using techniques that may have relatively limited resolution capabilities.Type: ApplicationFiled: May 15, 2009Publication date: May 20, 2010Inventors: Patrick Smith, Criswell Choi, James Montague Cleeves, Vivek Subramanian, Arvind Kamath, Steven Molesa
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Patent number: 7709307Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.Type: GrantFiled: August 21, 2007Date of Patent: May 4, 2010Assignee: Kovio, Inc.Inventors: Arvind Kamath, Patrick Smith, James Montague Cleeves
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Patent number: 7701011Abstract: An electronic device, including a substrate, a plurality of first semiconductor islands on the substrate, a plurality of second semiconductor islands on the substrate, a first dielectric film on the first subset of the semiconductor islands, second dielectric film on the second semiconductor islands, and a metal layer in electrical contact with the first and second semiconductor islands. The first semiconductor islands and the first dielectric film contain a first diffusible dopant, and the second semiconductor islands and the second dielectric layer film contain a second diffusible dopant different from the first diffusible dopant. The present electronic device can be manufactured using printing technologies, thereby enabling high-throughput, low-cost manufacturing of electrical circuits on a wide variety of substrates.Type: GrantFiled: August 3, 2007Date of Patent: April 20, 2010Assignee: Kovio, Inc.Inventors: Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Patrick Smith, Fabio Zürcher
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Patent number: 7687327Abstract: Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g.Type: GrantFiled: June 12, 2006Date of Patent: March 30, 2010Assignee: Kovio, Inc,Inventors: James Montague Cleeves, J. Devin MacKenzie, Arvind Kamath
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Patent number: 7619294Abstract: Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.Type: GrantFiled: October 28, 2005Date of Patent: November 17, 2009Assignee: LSI CorporationInventors: Venkatesh P. Gopinath, Arvind Kamath, Mohammad R. Mirabedini, Ming-Yi Lee
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Publication number: 20090137071Abstract: The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.Type: ApplicationFiled: October 10, 2008Publication date: May 28, 2009Inventors: Vivek SUBRAMANIAN, Patrick Smith, Vikram Pavate, Arvind Kamath, Criswell Choi, Aditi Chandra, James Montague Cleeves
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Publication number: 20090109035Abstract: The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.Type: ApplicationFiled: October 10, 2008Publication date: April 30, 2009Inventors: Vivek SUBRAMANIAN, Patrick Smith, Vikram Pavate, Arvind Kamath, Criswell Choi, Aditi Chandra, James Montague Cleeves
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Publication number: 20090085095Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature.Type: ApplicationFiled: October 1, 2008Publication date: April 2, 2009Inventors: Arvind KAMATH, Erik SCHER, Patrick SMITH, Aditi CHANDRA, Steven MOLESA
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Publication number: 20090065776Abstract: Embodiments relate to printing features from an ink containing a material precursor. In some embodiments, the material includes an electrically active material, such as a semiconductor, a metal, or a combination thereof. In another embodiment, the material includes a dielectric. The embodiments provide improved printing process conditions that allow for more precise control of the shape, profile and dimensions of a printed line or other feature. The composition(s) and/or method(s) improve control of pinning by increasing the viscosity and mass loading of components in the ink. An exemplary method thus includes printing an ink comprising a material precursor and a solvent in a pattern on the substrate; precipitating the precursor in the pattern to form a pinning line; substantially evaporating the solvent to form a feature of the material precursor defined by the pinning line; and converting the material precursor to the patterned material.Type: ApplicationFiled: May 2, 2008Publication date: March 12, 2009Inventors: Erik SCHER, Steven Molesa, Joerg Rockenberger, Arvind Kamath, Ikuo Mori
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Publication number: 20090020829Abstract: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. The method of forming contacts includes depositing an ink of a silicide-forming metal onto an exposed silicon surface, drying the ink to form a silicide-forming metal precursor, and heating the silicide-forming metal precursor and the silicon surface to form a metal silicide contact. Optionally, the metal precursor ink may be selectively deposited onto a dielectric layer adjacent to the exposed silicon surface to form a metal-containing interconnect. Furthermore, one or more bulk conductive metal(s) may be deposited on remaining metal precursor ink and/or the dielectric layer. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects.Type: ApplicationFiled: July 17, 2008Publication date: January 22, 2009Inventors: Aditi CHANDRA, Arvind KAMATH, James Montague CLEEVES, Joerg ROCKENBERGER, Mao Takashima, Erik SCHER
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Patent number: 7413996Abstract: A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an ion implanted species that causes lattice damage to the exposed portions of the high k layer. The lattice damaged exposed portions of the high k layer are etched to leave the high k gate insulation layer.Type: GrantFiled: April 14, 2003Date of Patent: August 19, 2008Assignee: LSI CorporationInventors: Arvind Kamath, Wai Lo, Venkatesh Gopinath
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Publication number: 20080048240Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.Type: ApplicationFiled: August 21, 2007Publication date: February 28, 2008Inventors: Arvind Kamath, Patrick Smith, James Montague Cleeves