Abstract: A thread management circuit of a processing system stores a thread identifier table and a thread completion table. The thread management circuit receives, from a processor core, a request for execution of a portion of an application by an accelerator circuit. The thread management circuit allocates a thread identifier available in the thread identifier table to the processor core for the execution of the portion by the accelerator circuit. The thread management circuit communicates a response and an acceleration request, both including the allocated thread identifier, to the processor core and the accelerator circuit, respectively. The thread management circuit communicates a thread joining response to the processor core based on a received thread joining request and an indication by the thread completion table that the execution of the portion by the accelerator circuit is complete. The executed portion is integrated with the application based on the thread joining response.

Abstract: An address fault detection system includes write and read access circuits and a fault management circuit. The write access circuit receives an address and reference data for a write operation associated with a memory and parity data generated based on the reference data, and writes the reference data and the parity data to first and second memory blocks of the memory, respectively. The read access circuit receives the same address for a read operation associated with the memory and reads another reference data and another parity data from the first and second memory blocks, respectively. The fault management circuit compares the read parity data with parity data generated based on the read reference data to detect an address fault in the memory. The written and read reference data are different when the address fault is detected, and same when the address fault is not detected.

Abstract: A transaction management system includes a storage circuit and a processing circuit. The storage circuit stores a current tag value of a tag ID of a device and a tag value associated with a transaction initiated by the device. The processing circuit receives a reset query to determine an availability of the device for reset. When the device is to be reset, the current tag value of the tag ID is updated. Further, the processing circuit generates an acknowledgment in response to the reset query such that the device is reset based on the acknowledgment. The updated tag ID ensures that responses for transactions that are initiated by the device before the reset are discarded.

Abstract: A transaction ordering system is configured to order various transactions initiated by one device for execution with another device. The transaction ordering system includes ordering circuitry that is configured to generate two pointer values such that one pointer value corresponds to a transaction identifier (ID) of a transaction that is to be processed, and another pointer value corresponds to a transaction ID of a latest initiated transaction. Based on the two pointer values, the ordering circuitry orders the transactions such that if a first transaction is initiated before a second transaction, a set of data packets associated with the first transaction is transmitted to the transaction initiating device before a set of data packets associated with the second transaction is transmitted.

Abstract: An integrated circuit (IC) includes a memory that stores a thread and a processor that generates an instruction request to retrieve one or more instructions of the thread. The IC further includes an error control circuit that receives the instruction request from the processor and retrieves an instruction of the thread from the memory based on the instruction request. Further, the error control circuit determines whether the retrieved instruction is erroneous. Based on the determination that the retrieved instruction is erroneous, the error control circuit provides a substitute instruction to the processor as a response to the instruction request. The substitute instruction is included in an instruction set of the processor. The processor executes the received substitute instruction and suspends an execution of the thread.

Abstract: A transaction management system includes a storage circuit and a processing circuit. The storage circuit stores a current tag value of a tag ID of a device and a tag value associated with a transaction initiated by the device. The processing circuit receives a reset query to determine an availability of the device for reset. When the device is to be reset, the current tag value of the tag ID is updated. Further, the processing circuit generates an acknowledgment in response to the reset query such that the device is reset based on the acknowledgment. The updated tag ID ensures that responses for transactions that are initiated by the device before the reset are discarded.

Abstract: An address fault detection system includes write and read access circuits and a fault management circuit. The write access circuit receives an address and reference data for a write operation associated with a memory and parity data generated based on the reference data, and writes the reference data and the parity data to first and second memory blocks of the memory, respectively. The read access circuit receives the same address for a read operation associated with the memory and reads another reference data and another parity data from the first and second memory blocks, respectively. The fault management circuit compares the read parity data with parity data generated based on the read reference data to detect an address fault in the memory. The written and read reference data are different when the address fault is detected, and same when the address fault is not detected.

Abstract: First and second processors that are in communication with each other are disclosed. The first processor includes a sampling controller, a sampling circuit, and a data flow controller. The sampling controller is configured to receive multiple identifiers and corresponding enable signals associated with data that is to be transmitted to or received from the second processor, and generate an identification signal and a sampling signal based on one of the identifiers and the corresponding enable signal. The sampling circuit is configured to sample multiple data counts to generate corresponding sampled counts based on the identification signal and the sampling signal. The data flow controller is configured to generate a control signal based on the identifiers, the corresponding enable signals, the data counts, and the corresponding sampled counts to control data flow between the first and second processors.

Abstract: An arbitration between a plurality of flows for access to a shared resource is disclosed. The plurality of flows may be associated with a single channel or multiple channels. When the plurality of flows are associated with a single channel, one flow is selected from the plurality of flows for accessing the shared resource based on flow priority levels associated with flows that are currently arbitrating for the access. Flow data associated with the selected flow is then outputted for granting the access. When the plurality of flows are associated with multiple channels, a flow associated with each channel is selected based on the flow priority levels. Further, a channel is selected based on channel priority levels of channels that are currently arbitrating for the access. Based on the selected channel, flow data associated with one of the selected flows is outputted for granting the access to the shared resource.

Abstract: A transaction ordering system is configured to order various transactions initiated by one device for execution with another device. The transaction ordering system includes ordering circuitry that is configured to generate two pointer values such that one pointer value corresponds to a transaction identifier (ID) of a transaction that is to be processed, and another pointer value corresponds to a transaction ID of a latest initiated transaction. Based on the two pointer values, the ordering circuitry orders the transactions such that if a first transaction is initiated before a second transaction, a set of data packets associated with the first transaction is transmitted to the transaction initiating device before a set of data packets associated with the second transaction is transmitted.

Abstract: A thread management circuit of a processing system stores a thread identifier table and a thread completion table. The thread management circuit receives, from a processor core, a request for execution of a portion of an application by an accelerator circuit. The thread management circuit allocates a thread identifier available in the thread identifier table to the processor core for the execution of the portion by the accelerator circuit. The thread management circuit communicates a response and an acceleration request, both including the allocated thread identifier, to the processor core and the accelerator circuit, respectively. The thread management circuit communicates a thread joining response to the processor core based on a received thread joining request and an indication by the thread completion table that the execution of the portion by the accelerator circuit is complete. The executed portion is integrated with the application based on the thread joining response.

Abstract: First and second processors that are in communication with each other are disclosed. The first processor includes a sampling controller, a sampling circuit, and a data flow controller. The sampling controller is configured to receive multiple identifiers and corresponding enable signals associated with data that is to be transmitted to or received from the second processor, and generate an identification signal and a sampling signal based on one of the identifiers and the corresponding enable signal. The sampling circuit is configured to sample multiple data counts to generate corresponding sampled counts based on the identification signal and the sampling signal. The data flow controller is configured to generate a control signal based on the identifiers, the corresponding enable signals, the data counts, and the corresponding sampled counts to control data flow between the first and second processors.

Abstract: An arbitration between a plurality of flows for access to a shared resource is disclosed. The plurality of flows may be associated with a single channel or multiple channels. When the plurality of flows are associated with a single channel, one flow is selected from the plurality of flows for accessing the shared resource based on flow priority levels associated with flows that are currently arbitrating for the access. Flow data associated with the selected flow is then outputted for granting the access. When the plurality of flows are associated with multiple channels, a flow associated with each channel is selected based on the flow priority levels. Further, a channel is selected based on channel priority levels of channels that are currently arbitrating for the access. Based on the selected channel, flow data associated with one of the selected flows is outputted for granting the access to the shared resource.

Abstract: A transaction controller orders transactions between a master device and a slave device, where the transactions may be received out-of-order. First and second transactions have respective first and second sets of data packets. The transaction controller includes a transaction table, a first ordering counter, and a first sequence counter having first and second values when the first and second transactions are initiated. The first and second values are stored in the transaction table based on first and second transaction identifiers (TIDs) that are associated with the first and second transactions. The transaction controller determines, based on the second value, the second TID, and a current value of the first ordering counter, whether the first and second sets of data packets were received out-of-order. Based on the determination, the second set of data packets is transmitted to the master device after the first set of data packets.

Abstract: A context switching system includes a processor and a scheduler. The processor is configured to execute a first thread. A first context associated with the first thread is stored in a register set of the processor. While the first thread is being executed, the scheduler is configured to select a second thread from a set of threads, and receive and store a second context associated with the second thread in a register set of the scheduler. The second thread is to be scheduled for execution after the first thread. The scheduler is further configured to swap the first and second contexts when the execution of the first thread is halted, thereby executing the context switching. Further, the processor is configured to execute the second thread based on the second context. While the second thread is being executed, the first context is stored in the data memory.

Abstract: In a hardware-accelerated computing systems, calls are made from a processor to an accelerator core. The hardware-accelerated computing system includes a processor core having a stack, an accelerator, and an accelerator scheduler. The computing system is configured to process an accelerator command by the processor core issuing an accelerator command to the accelerator scheduler during execution of a task the accelerator scheduler receiving the accelerator command and requesting data from the stack, the processor sending the requested data from the stack to the accelerator scheduler, the accelerator scheduler sending the requested data to the accelerator and sending a write response to the processor, the accelerator processing the accelerator command, and the processor continuing execution of the task. The processor pauses execution of the task upon issuing the accelerator command and resumes execution of the task upon receiving the write response from the accelerator scheduler.

Abstract: In at least one embodiment, a method for handling data units in a multi-user system includes granting a shared resource to a user of a plurality of users for a transaction associated with an entry of a transaction data structure. The method includes determining whether the transaction stored last partial data of a data unit associated with the user in an alignment register associated with the user. The method includes asserting a request for arbitration of a plurality of transactions associated with the plurality of users. The request is asserted for an additional transaction associated with the entry in response to determining that the transaction stored the last partial data in the alignment register. The method may include flushing the last partial data from the alignment register to a target memory in response to detecting an additional grant of the shared resource to the user for the additional transaction.

Abstract: In at least one embodiment, a method for handling data units in a multi-user system includes granting a shared resource to a user of a plurality of users for a transaction associated with an entry of a transaction data structure. The method includes determining whether the transaction stored last partial data of a data unit associated with the user in an alignment register associated with the user. The method includes asserting a request for arbitration of a plurality of transactions associated with the plurality of users. The request is asserted for an additional transaction associated with the entry in response to determining that the transaction stored the last partial data in the alignment register. The method may include flushing the last partial data from the alignment register to a target memory in response to detecting an additional grant of the shared resource to the user for the additional transaction.

Abstract: A transaction controller orders transactions between a master device and a slave device, where the transactions may be received out-of-order. First and second transactions have respective first and second sets of data packets. The transaction controller includes a transaction table, a first ordering counter, and a first sequence counter having first and second values when the first and second transactions are initiated. The first and second values are stored in the transaction table based on first and second transaction identifiers (TIDs) that are associated with the first and second transactions. The transaction controller determines, based on the second value, the second TID, and a current value of the first ordering counter, whether the first and second sets of data packets were received out-of-order. Based on the determination, the second set of data packets is transmitted to the master device after the first set of data packets.

Abstract: A wireless communication device selectively flushes frames from a processing pipeline on a per-user basis. The wireless communication device stores frames (e.g., physical layer service data units (PSDUs)) of data for processing at one or more queues, wherein each frame is stored with the tag of the user associated with the frame. In response to an exception, such as a detected error or a user-reset request, the wireless communication device changes the tag of the user associated with the exception. When a frame is selected from a queue for processing at a pipeline, the wireless communication device compares the stored tag associated with the frame with the current tag associated with the user corresponding to the frame. In response to a mismatch, the wireless communication device discards the frame.