Abstract: An integrated circuit (IC) in an unresponsive radio equipment (RE) node includes a common public radio interface (CPRI) controller, a processor, and a system reset controller that includes an L1 (Layer 1) reset controller. The CPRI controller generates a reset request signal based on a CPRI reset request received from an RE controller (REC). The L1 reset controller generates a traffic stop signal based on the reset request signal. The CPRI controller generates a traffic idle signal based on the traffic stop signal. The L1 reset controller receives the traffic idle signal before a predetermined time period and generates a system reset signal for resetting the processor, thereby recovering the unresponsive RE node without disrupting the network topology of a communication system that includes the REC and multiple RE nodes including the unresponsive RE node connected via a CPRI link.

Abstract: A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock.

Abstract: A system for calibrating a power amplifier (PA) includes a memory, a processor, a digital pre-distorter (DPD), and a data converter. The DPD includes a programming interface module, a pattern generator, a multiplier, and a pre-distorter module. The multiplier multiplies reference baseband stream data from the memory with pattern coefficient data generated by the pattern generator to generate shaped reference baseband stream data. The pre-distorter module generates pre-distorted shaped reference baseband stream data. The PA receives a low-power reference radio frequency (RF) signal corresponding to the pre-distorted shaped reference baseband stream data and generates a high-power reference RF signal.

Abstract: Adding a new subsystem node to a multi-node base station topology (e.g., a chain or tree topology) in a telecommunications network can disrupt the effective operation of the existing multi-node base station. By accurately measuring the timing difference between uplink and downlink signaling across a current terminating node during the configuration of the new terminating node, the new node can be added with reduced impact upon the operation of the existing base station nodes.

Abstract: A digital pre-distorter (DPD) for an RF transceiver system having multiple antennas includes a DPD controller, first and second address generators, stream select and antenna select muxes, first and second lookup tables (LUTs), first and second dynamic routing logic units, multipliers, an adder, and an accumulator. The DPD controller generates antenna select, stream select and stream routing signals indicative of selection of antennas, the first and second LUTs, and input signals. The DPD controller configures the DPD to share the multipliers and the first and second LUTs between multiple antennas by providing the antenna select signal to the antenna select mux, the stream select signal to the stream select mux, and the stream routing signals to the first and second dynamic routing logic units.

Abstract: A transmission node for use in a wireless communication network includes a first CPRI unit for transmitting auxiliary data to a second CPRI unit in the transmission node. A memory unit stores control word data of the auxiliary data. A memory write block is connected between the first CPRI unit and the memory unit for writing the control word data to the memory unit based on a first set of frame timing signals received from the first CPRI unit. A memory read and merge block is connected to the memory unit for reading the control word data stored in the memory unit based on a second set of frame timing signals, merging the control word data with IQ data, and transmitting the merged auxiliary data to the second CPRI unit.

Abstract: A system for reducing in-phase and quadrature-phase (I/Q) impairments includes first, second, third, and fourth programmable registers for storing respective first, second, third, and fourth values, first and second finite impulse response (FIR) filters having respective first and second sets of filter taps, and first and second adders. The first FIR filter receives an I input signal and generates first and second intermediate output signals based on the first and second values for I and Q channels, respectively. The second FIR filter receives a Q input signal and generates third and fourth intermediate output signals based on the third and fourth values for the I and Q channels, respectively. The first and second adders receive the first and second, and the third and fourth intermediate output signals, respectively, and generate compensated I and Q output signals for the I and Q channels.

Abstract: Adding a new subsystem node to a multi-node base station topology (e.g., a chain or tree topology) in a telecommunications network can disrupt the effective operation of the existing multi-node base station. By accurately measuring the timing difference between uplink and downlink signaling across a current terminating node during the configuration of the new terminating node, the new node can be added with reduced impact upon the operation of the existing base station nodes.

Abstract: A transmission node for use in a wireless communication network includes a first register for storing a set of first mask bits, a second register for storing a set of second mask bits, and a mask switching block for multiplexing the set of first mask bits and the set of second mask bits and outputting the set of third mask bits. The transmission node further includes a CPRI unit with an auxiliary interface for receiving the set of third mask bits. An activation block is connected between the CPRI unit and the mask switching block for causing the mask switching block to output the set of second mask bits based on data in a current frame in the CPRI unit.

Abstract: A transmission node for use in a wireless communication network includes a first register for storing a set of first mask bits, a second register for storing a set of second mask bits, and a mask switching block for multiplexing the set of first mask bits and the set of second mask bits and outputting the set of third mask bits. The transmission node further includes a CPRI unit with an auxiliary interface for receiving the set of third mask bits. An activation block is connected between the CPRI unit and the mask switching block for causing the mask switching block to output the set of second mask bits based on data in a current frame in the CPRI unit.

Abstract: A transmission node for use in a wireless communication network includes a first CPRI unit for transmitting auxiliary data to a second CPRI unit in the transmission node. A memory unit stores control word data of the auxiliary data. A memory write block is connected between the first CPRI unit and the memory unit for writing the control word data to the memory unit based on a first set of frame timing signals received from the first CPRI unit. A memory read and merge block is connected to the memory unit for reading the control word data stored in the memory unit based on a second set of frame timing signals, merging the control word data with IQ data, and transmitting the merged auxiliary data to the second CPRI unit.

Abstract: A method and apparatus automatically controls the insertion of information flow data over a shared CPRI link (561) by providing a hardware control mechanism (504-509) at a local radio base station subsystem (501) connected in a CPRI daisy chain configuration between a downstream RE device (570) and an upstream REC device (560) for determining whether the control word being transmitted is sourced from a downstream device (e.g., forwarded data from a downstream RE device) or from the local device.