Abstract: A wireless communication device selectively flushes frames from a processing pipeline on a per-user basis. The wireless communication device stores frames (e.g., physical layer service data units (PSDUs)) of data for processing at one or more queues, wherein each frame is stored with the tag of the user associated with the frame. In response to an exception, such as a detected error or a user-reset request, the wireless communication device changes the tag of the user associated with the exception. When a frame is selected from a queue for processing at a pipeline, the wireless communication device compares the stored tag associated with the frame with the current tag associated with the user corresponding to the frame. In response to a mismatch, the wireless communication device discards the frame.

Abstract: A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. The packet processor generates a transmit control configuration packet, which includes the control data. The control-frame processor inserts the transmit control configuration packet into a first control frame, outputs the control frame to the interface and extracts a receive-configuration packet from a second control frame for generating one or more interrupts. The mode selector generates mode and idle signals for determining the mode of the interface, based on the idle signal. In one implementation, the system uses JESD control frames to reduce GPIO pin usage.

Abstract: An apparatus for reception and detection of RACH data in an LTE input signal includes a hardware accelerator that has a decimator that filters and down-samples the input signal, a first Fourier transform circuit that transforms the decimated signal from the time domain to the frequency domain, and a second transform circuit that multiplies the resulting signal by a complex Z-C sequence and performs an inverse Fourier transform (iFT) operation to transform the multiplied signal from the frequency domain to the time domain. A DSP performs a delay profile analysis operation on the signal resulting from the iFT operation.

Abstract: An eNode-B includes PUSH mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. A buffer receives and stores first and second identifiers. A de-multiplexer outputs a first code word number based on the first identifier and a second code word number based on the second identifier. A set of completion queues store the first and second code word numbers. A sequence controller generates first and second select signals corresponding to the first and second identifiers. A multiplexer outputs one of the first and second code word numbers based on the select signals, and the scheduler schedules the first and second code words based on the first and second identifiers.

Abstract: A FIR filter includes segment cells, each of which is configurable as an interpolation filter, a decimation filter, a symmetric filter, or an asymmetric filter. Two or more of the segment cells are configurable to be cascaded to form an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, or a complex asymmetric filter. The FIR filter includes registers corresponding to the segment cells for storing coefficient values of the corresponding segment cells. The FIR filter further includes control circuits corresponding to the segment cells for generating control signals.

Abstract: A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. The packet processor generates a transmit control configuration packet, which includes the control data. The control-frame processor inserts the transmit control configuration packet into a first control frame, outputs the control frame to the interface and extracts a receive-configuration packet from a second control frame for generating one or more interrupts. The mode selector generates mode and idle signals for determining the mode of the interface, based on the idle signal. In one implementation, the system uses JESD control frames to reduce GPIO pin usage.

Abstract: An eNode-B includes PUSH mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. A buffer receives and stores first and second identifiers. A de-multiplexer outputs a first code word number based on the first identifier and a second code word number based on the second identifier. A set of completion queues store the first and second code word numbers. A sequence controller generates first and second select signals corresponding to the first and second identifiers. A multiplexer outputs one of the first and second code word numbers based on the select signals, and the scheduler schedules the first and second code words based on the first and second identifiers.

Abstract: A base transceiver station (BTS) includes dedicated memories to store uplink real-time (RT) data received by way of an antenna of the BTS and downlink RT data generated by processors of the BTS. The dedicated memories serve a dedicated number of processors, which prevents over-run and under-run of antenna buffers and provides deterministic data flow necessary to stream time-critical uplink and downlink RT data. Thus, a high and dedicated bandwidth for the uplink and downlink RT data is ensured.

Abstract: A system for mapping control and user data includes a direction scanner, an address calculator, a collision detector, a buffer, and a mapper for mapping control and user data from a first memory to a second memory. The direction scanner determines the highest priority value of to a code word index. The address calculator calculates start and end addresses of the highest priority value. When an address from an address range, defined by the start and end addresses, is already mapped to other control data, the collision detector detects a collision and generates feedback data. The address calculator outputs modified start and end addresses based on the feedback data. When no collision is detected, the address calculator outputs the modified start and end addresses to the buffer. The mapper then maps the control and user data to the modified start and end addresses in the second memory.

Abstract: An apparatus for reception and detection of RACH data in an LTE input signal includes a hardware accelerator that has a decimator that filters and down-samples the input signal, a first Fourier transform circuit that transforms the decimated signal from the time domain to the frequency domain, and a second transform circuit that multiplies the resulting signal by a complex Z-C sequence and performs an inverse Fourier transform (iFT) operation to transform the multiplied signal from the frequency domain to the time domain. A DSP performs a delay profile analysis operation on the signal resulting from the iFT operation.

Abstract: A base transceiver station (BTS) includes dedicated memories to store uplink real-time (RT) data received by way of an antenna of the BTS and downlink RT data generated by processors of the BTS. The dedicated memories serve a dedicated number of processors, which prevents over-run and under-run of antenna buffers and provides deterministic data flow necessary to stream time-critical uplink and downlink RT data. Thus, a high and dedicated bandwidth for the uplink and downlink RT data is ensured.

Abstract: A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.

Abstract: A system for merging first and second interrupts includes first and second queue modules, first and second status modules, and first and second merger modules. The first and second queue modules receive first and second en-queue signals corresponding to the first and second interrupts, first and second de-queue signals, and generate first and second status signals. The first and second status modules receive first and second status signals, and first and second output signals, and generate first and second merge signals. The first and second merger modules receive the first and second merge signals, and generate the first and second output signals. One of the first and second output signals is indicative of the first and second en-queue signals, thereby merging the first and second interrupts into at least one of the first and second output signals.

Abstract: A FIR filter includes segment cells, each of which is configurable as an interpolation filter, a decimation filter, a symmetric filter, or an asymmetric filter. Two or more of the segment cells are configurable to be cascaded to form an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, or a complex asymmetric filter. The FIR filter includes registers corresponding to the segment cells for storing coefficient values of the corresponding segment cells. The FIR filter further includes control circuits corresponding to the segment cells for generating control signals.

Abstract: For a baseband digital front-end (BDFE) processor that communicates with one or more radio-frequency integrated circuit (RFIC) chips over two or more JESD-compliant links in a multi-antenna base station, the BDFE has JESD transmitters (TXs) and receivers (RXs) that transmit and receive data to and from the RFIC chips and a time-based generator (TBGEN) that generates sync and idle signals that ensure that the processing of the different JESD TXs and RXs are aligned in time for data associated with a single logical group of antennas. The TBGEN has hardware-based alignment circuitry that generates the sync and idle signals, thereby avoiding the latency and unpredictability inherent with software-based solutions.

Abstract: A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock.

Abstract: A system for merging first and second interrupts includes first and second queue modules, first and second status modules, and first and second merger modules. The first and second queue modules receive first and second en-queue signals corresponding to the first and second interrupts, first and second de-queue signals, and generate first and second status signals. The first and second status modules receive first and second status signals, and first and second output signals, and generate first and second merge signals. The first and second merger modules receive the first and second merge signals, and generate the first and second output signals. One of the first and second output signals is indicative of the first and second en-queue signals, thereby merging the first and second interrupts into at least one of the first and second output signals.

Abstract: A method and apparatus automatically controls the insertion of information flow data over a shared CPRI link (561) by providing a hardware control mechanism (504-509) at a local radio base station subsystem (501) connected in a CPRI daisy chain configuration between a downstream RE device (570) and an upstream REC device (560) for determining whether the control word being transmitted is sourced from a downstream device (e.g., forwarded data from a downstream RE device) or from the local device.

Abstract: A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.

Abstract: A fractional and integer ratio polyphase interpolation filter changes the sample rate of an input digital signal by a ratio defined by an interpolation rate, M, and a decimation rate, N. The clock rate required to evaluate the output signal is M/N.