Patents by Inventor Arvind Kumar

Arvind Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210357138
    Abstract: In a deep neural network (DNN), weights are defined that represent a strength of connections between different neurons of the DNN and activations are defined that represent an output produced by a neuron after passing through an activation function of receiving an input and producing an output based on some threshold value. The weight traffic associated with a hybrid memory therefore is distinguished from the activation traffic to the hybrid memory, and one or more data structures may be dynamically allocated in the hybrid memory according to the weights and activations of the or more data structures in the DNN. The hybrid memory includes at least a first memory and a second memory that differ according to write endurance attributes.
    Type: Application
    Filed: May 13, 2020
    Publication date: November 18, 2021
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashish RANJAN, Arvind KUMAR, Carl RADENS
  • Patent number: 11177217
    Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
  • Patent number: 11175844
    Abstract: In a deep neural network (DNN), weights are defined that represent a strength of connections between different neurons of the DNN and activations are defined that represent an output produced by a neuron after passing through an activation function of receiving an input and producing an output based on some threshold value. The weight traffic associated with a hybrid memory therefore is distinguished from the activation traffic to the hybrid memory, and one or more data structures may be dynamically allocated in the hybrid memory according to the weights and activations of the one or more data structures in the DNN. The hybrid memory includes at least a first memory and a second memory that differ according to write endurance attributes.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashish Ranjan, Arvind Kumar, Carl Radens
  • Publication number: 20210344198
    Abstract: A method of operating a power generation system (100) employing a generator (110) and a solar power source (120) is provided. The method includes the steps of determining (310) if a wind speed is less than a cut-in speed, calculating (315) a reactive power demand for an electrical grid (102), calculating (320) a reactive power capability of a line side converter (140), determining (325) if the reactive power demand is greater than the reactive power capability, and calculating (330) a reactive power capability of the line side converter (140) and a rotor side converter (130). The method also includes the steps of determining (335) if the reactive power demand is greater than the reactive power capability of the line side converter (140) and the rotor side converter (130), and reducing solar power generation or reconfiguring the line side converter (140) and/or the rotor side converter (130) to meet reactive power demand.
    Type: Application
    Filed: September 5, 2019
    Publication date: November 4, 2021
    Inventors: Arvind Kumar Tiwari, Vaidhya Nath Venkitanarayanan, Yashomani Yashodhan Kolhatkar, Veena Padma Rao
  • Publication number: 20210342489
    Abstract: A technique relates to biasing, using a control system, a crossbar array of resistive processing units (RPUs) under a midrange condition, the midrange condition causing resistances of the RPUs to result in a random output of low values and high values in about equal proportions. The control system reinforces the low values and the high values of the random output by setting the resistances of the RPUs to a state that forces the low values and the high values having resulted from the midrange condition. Reinforcing the low values and the high values makes the random output permanent even when the crossbar array of the RPUs is not biased under the midrange condition. The control system records a sequence of the low values and the high values of the random output responsive to reinforcing the low values and the high values of the random output.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 4, 2021
    Inventors: Arvind Kumar, Takashi Ando, Dirk Pfeiffer
  • Patent number: 11163707
    Abstract: Embodiments of the present invention describe a hierarchical cortical emulation using a scratchpad memory device and a storage class memory device. The scratchpad memory device is partitioned into a first subset of memory locations and a second subset of memory locations. A processor from a neural network device is assigned a first memory portion from the first subset, a second memory portion from the second subset, and a third memory portion from the storage class memory device. Further the neural network device and a memory controller perform a compute cycle for a hierarchical level k, 1?k?n, n being total number of levels. A compute cycle includes performing, by the processor, computations from the level k using neuron data stored in the first memory portion, and in parallel, copying by the memory controller, the neuron data for a hierarchical level k+1 from the third memory portion to the second memory portion.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arvind Kumar, Ahmet S. Ozcan, J. Campbell Scott
  • Publication number: 20210327524
    Abstract: In a memory system, receiver reference voltage adjustment per path provides the capability to adjust receiver reference voltages on a per path basis. Adjustment of receiver reference voltages for the memory device to an optimal receiver reference voltage per path is accomplished with dedicated mode registers and a local receiver voltage reference adjuster circuit in the memory device for each data path. The optimal receiver reference voltage is determined during training based on selected feedback per path from the memory device. The dedicated mode registers contain adjustment values that were previously programmed during training, and include adjustments steps to add to or subtract from a global receiver reference voltage for all paths until reaching the optimal receiver reference voltage for a current path.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 21, 2021
    Inventors: Arvind KUMAR, Dean-Dexter R. EUGENIO, John R. GOLES
  • Publication number: 20210324790
    Abstract: A new method and approach to have a compact engine having capability of running on both Fuel and Electricity. Engine will be capable of giving high power and better efficiency based on need. Engines can be operated together as well as independently while giving an option to choose the fuel, power and efficiency.
    Type: Application
    Filed: April 18, 2020
    Publication date: October 21, 2021
    Inventor: ARVIND KUMAR
  • Publication number: 20210326041
    Abstract: In a memory system, reference voltage training per path provides the capability to train receiver and transmitter reference voltages to optimal values based on selected feedback per path from the memory device. Training receiver reference voltages to an optimal receiver reference voltage per path includes programming dedicated mode registers that enable a local receiver voltage reference adjuster circuit to adjust the receiver reference voltage per path to the optimal receiver reference voltage per path. Transmitter reference voltage training includes the capability to also train an optimal input timing delay for an optimal transmitter reference voltage. Reference voltage training can be performed by a host component and/or a test system having access to the selected feedback per path of the memory device undergoing training.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 21, 2021
    Inventors: Arvind KUMAR, Dean-Dexter R. EUGENIO, John R. GOLES, Santhosh MUSKULA
  • Patent number: 11153104
    Abstract: Crossbar arrays (e.g., Resistive Processing Unit (RPU) accelerators) are leveraged to create a Physically Unclonable Function (PUF) that exploits variations, such as statistical process variation in manufacture or operation, to generate key material to secure information in a computing environment. One environment is a cloud compute infrastructure whose shared resources are used to process workloads. During RPU accelerator use, the state of the RPU's bits are changed by reproducible inputs, e.g., stochastic pulses applied to change resistive values in the array, and the corresponding changes in the RPU array state captured. These responses, which cannot be reproduced from another device due to random device variations across chips that embody the RPUs, are then used to generate (or facilitate generation of) the cryptographic material. In one embodiment, inputs applied to the RPU accelerator array are generated from a pseudo-random number generator that is otherwise associated with the RPU accelerator.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Shawn Peter Fetterolf, Arvind Kumar
  • Patent number: 11152787
    Abstract: A system of reactive power compensators for a wind farm includes a multi-winding transformer and a plurality of modular reactive power compensators (MVBs). The multi-winding transformer includes a primary winding and a plurality of secondary windings. The primary winding is configured to be coupled to a point of common coupling (POCC) for the wind farm. The plurality of MVBs are each coupled to a corresponding winding of the plurality of secondary windings.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: October 19, 2021
    Assignee: General Electric Company
    Inventors: Arvind Kumar Tiwari, Jayanti Navilgone Ganesh, Kasi Viswanadha Raju Gadiraju, Robert Gregory Wagoner, Harmeet Singh Narang
  • Publication number: 20210309641
    Abstract: Compounds and methods for the treatment of a bacterial infection or the potentiation of an antibiotic in treating a bacterial infection are described herein.
    Type: Application
    Filed: June 13, 2019
    Publication date: October 7, 2021
    Applicant: GEORGIA STATE UNIVERSITY RESEARCH FOUNDATION, INC.
    Inventors: Binghe Wang, David W. Boykin, Manjusha Roy Choudhury, Arvind Kumar, Bingchen Yu, Mengyuan Zhu
  • Publication number: 20210313391
    Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Arvind Kumar, Joshua M. Rubin
  • Patent number: 11133259
    Abstract: A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Rubin, Arvind Kumar, Lawrence A. Clevenger, Steven Lorenz Wright, Wiren Dale Becker, Xiao Hu Liu
  • Publication number: 20210296898
    Abstract: A system for controlling a hybrid power generation plant is provided. The system is programmed to receive current conditions at the plurality of power generating assets including a first asset type and a second asset type, determine a forecast for a period of time based at least in part on the current conditions, determine that a first asset of the first asset type of the plurality of power generating assets has an available uprate margin for production of a first amount of active power, determine that a second asset of the second asset type of the plurality of power generating assets has capacity to generate a second amount of reactive power, instruct the first asset to reduce production of reactive power by the second amount and increase production of active power by the first amount, and instruct the second asset to increase production of reactive power by the second amount.
    Type: Application
    Filed: March 19, 2020
    Publication date: September 23, 2021
    Inventors: Veena Padmarao, Arvind Kumar Tiwari, Aditya Vyas, Karen Emanuelle Hernandez Pagan
  • Patent number: 11127325
    Abstract: Technologies for performing a simplified pixel shifting scheme on a display (e.g., an organic light emitting diode (OLED) display) are disclosed herein. An electronic device presents, on the display, a virtual display having an active area and a margin area surrounding the active area. The active area is to display content (e.g., image data, video data, etc.), and an amount of pixels in the virtual display is greater than an amount of pixels in the active area. The electronic device is also to shift the pixels of the active area within the virtual display according to a pixel shifting technique and update a touch coordinate offset for the touch screen interface based on the shift.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Zhiming Zhuang, Jun Jiang, Arvind Kumar
  • Patent number: 11114963
    Abstract: A power generation system (100, 200, 300, 400) is presented. The power generation system includes a prime mover (102), a doubly-fed induction generator (DFIG) (104) having a rotor winding (126) and a stator winding (122), a rotor-side converter (106), a line-side converter (108), and a secondary power source (110, 401) electrically coupled to a DC-link (128). Additionally, the power generation system includes a control sub-system (112, 212, 312) having a controller, and a plurality of switching elements (130, and 132 or 201). The controller is configured to selectively control switching of one or more switching elements (130, and 132 or 201) based on a value of an operating parameter corresponding to at least one of the prime mover, the DFIG, or the secondary power source to connect the rotor-side converter in parallel to the line-side converter to increase an electrical power production by the power generation system.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 7, 2021
    Assignee: General Electric Company
    Inventors: Govardhan Ganireddy, Arvind Kumar Tiwari, Yashomani Y Kolhatkar, Anthony Michael Klodowski, John Leo Bollenbecker, Harold Robert Schnetzka, Robert Gregory Wagoner, Veena Padmarao
  • Publication number: 20210272402
    Abstract: A method can include obtaining access code data corresponding to an access code transmitted to a user device. The method can further include monitoring the user device. The method can further include determining, based on the monitoring, that the access code is shared. The method can further include initiating, in response to the determining that the access code is shared, an invalidation of the access code.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Inventors: Saurabh Yadav, Raghuveer Prasad Nagar, Arvind Kumar
  • Patent number: 11101318
    Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: August 24, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arvind Kumar, Joshua M. Rubin
  • Patent number: 11101357
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 24, 2021
    Assignee: Tessera, Inc.
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw