Abstract: A semiconductor device is provided which enables a flip chip connection without use of underfill. The semiconductor device includes a semiconductor element having circuit electrodes and a circuit surface coated with a protecting film. A stress relaxation layer is provided by coating a cured thermoplastic resin onto the protecting film of the circuit surface in a manner which leaves the circuit electrodes exposed and curing it and having an inclination in the edge portion thereof. A wiring layer with wirings is connected to each of the circuit electrodes and disposed so as to make an electrical connection from the circuit electrodes, via the edge portion of the stress relaxation layer, and to a desired portion on the surface of the stress relaxation layer. A protecting film is provided thereon, and an external connection terminal is also provided.

Abstract: In a small semiconductor device having external terminals on a semiconductor element and a semiconductor module mounted with the small semiconductor device, disconnection of the external terminals is prevented when a temperature change occurs under the conditions that the semiconductor device is mounted on a printed circuit board. To achieve this a projection is formed on a land which is an external terminal bonding area of the semiconductor device, and a protruded portion of the projection is bonded to the external terminal. An intervening portion of a protective film made of resin material is formed between the lands and semiconductor element.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: Semiconductor devices, semiconductor wafers, and semiconductor modules are provided, wherein: the semiconductor device has a small warp; damage at the chip edge and cracks occurring in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor includes a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on the same plane.

Abstract: A semiconductor device including a semiconductor element having external terminals at a first level and external electrodes at a second level, higher than the first level. The external terminals include power terminals, ground terminals and signal terminals formed on a main surface of the semiconductor element. The external electrodes include power electrodes connected to the power terminals via power connecting sections, ground electrodes connected to the ground terminals via ground connecting sections and signal electrodes connected to the signal terminals via signal connecting sections. One of the signal terminals, signal electrodes and corresponding signal connecting sections are surrounded by either the power connecting sections connecting the power terminals and power electrodes or by the ground connection sections connecting the ground terminals and ground electrodes.

Abstract: In the conventional bump forming method that can be applied to a semiconductor device in which a large number of bumps are required to be formed, there are various limitations on the material of which the bumps are made, due to enough cubic volume of bumps and to small scattering of the bump height. According to the invention, solder balls and a tool having a large number of through-holes are used, and under the condition that the through-holes of the tool are aligned with the pads of the semiconductor device, the solder balls are charged into the through-holes, pressed to be fixed on the pads, and then reflowed to form bumps.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.

Abstract: A semiconductor device including a semiconductor element having external terminals at a first level and external electrodes at a second level, higher than the first level. The external terminals include power terminals, ground terminals and signal terminals formed on a main surface of the semiconductor element. The external electrodes include power electrodes connected to the power terminals via power connecting sections, ground electrodes connected to the ground terminals via ground connecting sections and signal electrodes connected to the signal terminals via signal connecting sections. One of the signal terminals, signal electrodes and corresponding signal connecting sections are surrounded by either the power connecting sections connecting the power terminals and power electrodes or by the ground connection sections connecting the ground terminals and ground electrodes.

Abstract: In a multi chip module of a structure wherein a plurality of bare or packaged semiconductor chips are mounted on a single wiring board and upper surfaces of the semiconductor chips are covered with a single heat spread plate, the whole space around the semiconductor chips thus sandwiched between the wiring board and the heat spread plate is filled with resin.

Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

Abstract: A semiconductor apparatus comprising a semiconductor device, an electrically insulating layer formed on the semiconductor device, and an external connection terminal formed on the electrically insulating layer and electrically connected to an electrode of the semiconductor device, wherein a power/ground line and a signal line in a region of from an edge of the electrically insulating layer to a uniform-thickness flat portion of the electrically insulating layer are different in kind of wiring pattern from each other.

Abstract: Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells.

Abstract: Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility.

Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide &agr;-ray shielding of the semiconductor device.

Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.