Patents by Inventor Asao Nishimura
Asao Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020050636Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.Type: ApplicationFiled: October 23, 2001Publication date: May 2, 2002Inventors: Yukiharu Akiyama, Tomoaki Kudaishi, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Asao Nishimura, Ichiro Anjo, Kunihiro Tsubosaki, Chuichi Miyazaki, Hiroshi Koyama, Masanori Shibamoto, Akira Nagai, Masahiko Ogino
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Publication number: 20020047215Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.Type: ApplicationFiled: October 23, 2001Publication date: April 25, 2002Inventors: Yukiharu Akiyama, Tomoaki Kudaishi, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Asao Nishimura, Ichiro Anjo, Kunihiro Tsubosaki, Chuichi Miyazaki, Hiroshi Koyama, Masanori Shibamoto, Akira Nagai, Masahiko Ogino
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Publication number: 20020047179Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.Type: ApplicationFiled: November 20, 2001Publication date: April 25, 2002Inventors: Hiroya Shimizu, Asao Nishimura, Tosiho Miyamoto, Hideki Tanaka, Hideo Miura
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Publication number: 20020038907Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: ApplicationFiled: October 26, 2001Publication date: April 4, 2002Applicant: Hitachi, Ltd.Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
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Patent number: 6365439Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: GrantFiled: January 29, 2001Date of Patent: April 2, 2002Assignee: Hitachi, Ltd.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Patent number: 6355975Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: GrantFiled: January 30, 2001Date of Patent: March 12, 2002Assignee: Hitachi, Ltd.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Patent number: 6355500Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: GrantFiled: January 25, 2001Date of Patent: March 12, 2002Assignee: Hitachi. Ltd.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Patent number: 6353255Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: GrantFiled: January 19, 2001Date of Patent: March 5, 2002Assignee: Hitachi, Ltd.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Publication number: 20020025655Abstract: The present invention is a semiconductor device having the semiconductor element 1 obtained by cutting a semiconductor wafer with the electrode pad 2 formed on one side along the scribe line, the semiconductor element protective layer 7 on the semiconductor element 1 which has the opening 7(1) on the pad 2, the stress cushioning layer 3 on the layer 7 which has the opening 3(1) on the pad 2, the lead wire portion 4 reaching the layer 3 from the electrode pad 2 via the openings 7(1) and 3(1), the external electrodes 6 on the lead wire portion 4, and the conductor protective layer 5 on the layer 3 and the layer 7, the layer 3, and the conductor protective layer 5 form the respective end faces on the end surface 1(1) of the semiconductor element 1 inside the scribe line and expose the range from the end face of the end surface 1(1) to the inside of the scribe line.Type: ApplicationFiled: March 16, 2001Publication date: February 28, 2002Inventors: Toshiya Satoh, Masahiko Ogino, Tadanori Segawa, Yoshihide Yamaguchi, Hiroyuki Tenmei, Atsushi Kazama, Ichiro Anjo, Asao Nishimura
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Patent number: 6348741Abstract: A manufacturing method makes it possible to produce a semiconductor apparatus which is outstanding in mounting reliability at a high manufacturing yield rate. A semiconductor apparatus, in which, on the surface of a semiconductor chip with a circuit and an electrode formed thereon, a stress cushioning layer is provided, except for a part where the electrode is, has a wiring layer connected to the electrode on the stress cushioning layer, an external protection film on the wiring layer and stress cushioning layer, a window where a part of the wiring layer is exposed at a predetermined location of the external protection film, and an external electrode which is electrically connected to the wiring layer via the window. The stress cushioning layer, wiring layer, conductor, external protection film, and external electrode are formed on the inside of the end of the semiconductor chip.Type: GrantFiled: September 29, 2000Date of Patent: February 19, 2002Assignee: Hitachi, Ltd.Inventors: Masahiko Ogino, Takao Miwa, Toshiya Satoh, Akira Nagai, Tadanori Segawa, Akihiro Yaguchi, Ichiro Anjo, Asao Nishimura, Takumi Ueno
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Publication number: 20020019077Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.Type: ApplicationFiled: October 9, 2001Publication date: February 14, 2002Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
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Publication number: 20020019146Abstract: A semiconductor device produced by forming an oxide film on a substrate, heat treating the oxide film at a temperature of 800° C. or higher in an inert atmosphere, followed by conventional steps for formation of a transistor, is improved in electrical reliability due to relaxation of stress generated in the oxide film or in the surface of substrate.Type: ApplicationFiled: October 16, 2001Publication date: February 14, 2002Inventors: Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasuhide Hagiwara, Hiroyuki Ohta, Asao Nishimura
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Publication number: 20020013038Abstract: A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.Type: ApplicationFiled: March 16, 2001Publication date: January 31, 2002Inventors: Hideo Miura, Shunji Moribe, Hisayuki Kato, Atsuyoshi Koike, Shuji Ikeda, Asao Nishimura
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Patent number: 6342728Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: GrantFiled: January 17, 2001Date of Patent: January 29, 2002Assignee: Hitachi, Ltd.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Patent number: 6342726Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: GrantFiled: November 26, 1999Date of Patent: January 29, 2002Assignee: Hitachi, Ltd.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Publication number: 20020009610Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.Type: ApplicationFiled: October 9, 2001Publication date: January 24, 2002Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
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Patent number: 6335565Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: GrantFiled: July 30, 1999Date of Patent: January 1, 2002Assignee: Hitachi, Ltd.Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
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Patent number: 6326681Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.Type: GrantFiled: January 13, 2000Date of Patent: December 4, 2001Assignee: Hitachi, LTDInventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
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Patent number: 6326699Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.Type: GrantFiled: December 8, 2000Date of Patent: December 4, 2001Assignee: Hitachi, Ltd.Inventors: Hiroya Shimizu, Asao Nishimura, Tosiho Miyamoto, Hideki Tanaka, Hideo Miura
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Patent number: RE37690Abstract: A lead frame and a semiconductor device wherein a through hole is formed in the center of a semiconductor chip-mounting surface of a chip pad at the center of the lead frame, the through hole being tapered or being one which corresponds to a surface area that is greater on the surface of the chip-mounting surface of the chip pad than on the surface of the side opposite to the chip-mounting surface thereof. This prevents the occurrence of cracks in the sealing plastic portion in the step of reflow soldering of the lead frame to the substrate.Type: GrantFiled: May 24, 1995Date of Patent: May 7, 2002Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Sueo Kawai, Asao Nishimura, Hideo Miura, Akihiro Yaguchi, Chikako van Koten nee Kitabayashi, Ichio Shimizu, Toshio Hatsuda, Toshinori Ozaki, Toshio Hattori, Souji Sakata