Patents by Inventor Asao Yamashita
Asao Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9022225Abstract: Provided is a filtration filer with which a stable opening size during filtration is obtained, and which can be easily regenerated when clogged and used repeatedly. The filtration filter (10) comprises: a substrate stack wherein substrates (11) that have a through hole that penetrates from front to back are stacked; stoppers (15) that define the spacing between the substrates (11); and pillars (16) with a larger thermal expansion coefficient than the stoppers (15). The spacing between the substrates (11) at normal temperature is defined at least by the stoppers (15), and the spacing when heated is defined by the thermally expanded pillars (16). The gaps between the substrates (11) form the filtration surface that traps contaminants contained in the liquid that is being treated A.Type: GrantFiled: March 13, 2012Date of Patent: May 5, 2015Assignee: Tokyo Electron LimitedInventors: Tsuyoshi Moriya, Asao Yamashita
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Publication number: 20140008290Abstract: Provided is a filtration filer with which a stable opening size during filtration is obtained, and which can be easily regenerated when clogged and used repeatedly. The filtration filter (10) comprises: a substrate stack wherein substrates (11) that have a through hole that penetrates from front to back are stacked; stoppers (15) that define the spacing between the substrates (11); and pillars (16) with a larger thermal expansion coefficient than the stoppers (15). The spacing between the substrates (11) at normal temperature is defined at least by the stoppers (15), and the spacing when heated is defined by the thermally expanded pillars (16). The gaps between the substrates (11) form the filtration surface that traps contaminants contained in the liquid that is being treated A.Type: ApplicationFiled: March 13, 2012Publication date: January 9, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Tsuyoshi Moriya, Asao Yamashita
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Patent number: 8501628Abstract: A method for etching a differential metal gate structure on a substrate is described. The differential metal gate structure includes a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein the metal gate layer comprises a different thickness at different regions on the substrate. The metal gate layer is patterned by using a plasma etching process, wherein at least one etch step includes forming plasma using a halogen-containing gas and at least one etch step includes forming plasma using an additive gas having as atomic constituents C, H, and F.Type: GrantFiled: March 23, 2010Date of Patent: August 6, 2013Assignee: Tokyo Electron LimitedInventors: Vinh Hoang Luong, Hiroyuki Takahashi, Akiteru Ko, Asao Yamashita, Vaidya Bharadwaj, Takashi Enomoto, Daniel J. Prager
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Patent number: 8251011Abstract: An apparatus, which performs a plasma process on a target substrate by using plasma, includes first and second electrodes in a process chamber to oppose each other. An RF field, which turns a process gas into plasma by excitation, is formed between the first and second electrodes. An RF power supply, which supplies RF power, is connected to the first or second electrode through a matching circuit. The matching circuit automatically performs input impedance matching relative to the RF power. A variable impedance setting section is connected to a predetermined member, which is electrically coupled with the plasma, through an interconnection. The impedance setting section sets a backward-direction impedance against an RF component input to the predetermined member from the plasma. A controller supplies a control signal concerning a preset value of the backward-direction impedance to the impedance setting section.Type: GrantFiled: May 31, 2007Date of Patent: August 28, 2012Assignee: Tokyo Electron LimitedInventors: Yohei Yamazawa, Manabu Iwata, Chishio Koshimizu, Fumihiko Higuchi, Akitaka Shimizu, Asao Yamashita, Nobuhiro Iwama, Tsutomu Higashiura, DongSheng Zhang, Michiko Nakaya, Norikazu Murakami
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Patent number: 8183062Abstract: The invention can provide apparatus and methods of creating metal gate structures on wafers in real-time using Lithography-Etch-Lithography-Etch (LELE) processing sequence. Real-time data and/or historical data associated with LELE processing sequences can be fed forward and/or fed back as fixed variables or constrained variables in internal-Integrated-Metrology modules (i-IMM) to improve the accuracy of the metal gate structures.Type: GrantFiled: February 24, 2009Date of Patent: May 22, 2012Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager
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Patent number: 8175736Abstract: A processing system and method for chemical oxide removal (COR) is presented, wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.Type: GrantFiled: December 9, 2010Date of Patent: May 8, 2012Assignee: Tokyo Electron LimitedInventors: Masayuki Tomoyasu, Merritt Funk, Kevin A. Pinto, Masaya Odagiri, Lemuel Chen, Asao Yamashita, Akira Iwami, Hiroyuki Takahashi
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Publication number: 20110307089Abstract: A processing system and method for chemical oxide removal (COR) is presented, wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.Type: ApplicationFiled: December 9, 2010Publication date: December 15, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Masayuki TOMOYASU, Merritt Lane Funk, Kevin Augustine Pinto, Masaya Odagiri, Lemuel Chen, Asao Yamashita, Akira Iwami, Hiroyuki Takahashi
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Publication number: 20110237084Abstract: A method for etching a differential metal gate structure on a substrate is described. The differential metal gate structure includes a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein the metal gate layer comprises a different thickness at different regions on the substrate. The metal gate layer is patterned by using a plasma etching process, wherein at least one etch step includes forming plasma using a halogen-containing gas and at least one etch step includes forming plasma using an additive gas having as atomic constituents C, H, and F.Type: ApplicationFiled: March 23, 2010Publication date: September 29, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Vinh Hoang LUONG, Hiroyuki TAKAHASHI, Akiteru KO, Asao YAMASHITA, Vaidyanathan BALASUBRAMANIAM, Takashi ENOMOTO, Daniel J. PRAGER
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Patent number: 8019458Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.Type: GrantFiled: August 6, 2008Date of Patent: September 13, 2011Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee
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Patent number: 7967995Abstract: The invention provides a method of processing a substrate using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more masking layer creation procedures, one or more pre-processing measurement procedures, one or more Partial-Etch (P-E) procedures, one or more Final-Etch (F-E) procedures, and one or more post-processing measurement procedures.Type: GrantFiled: March 31, 2008Date of Patent: June 28, 2011Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Radha Sundararajan, Hyung Joo Lee, Daniel Prager, Asao Yamashita
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Patent number: 7939450Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.Type: GrantFiled: September 21, 2007Date of Patent: May 10, 2011Assignee: Tokyo Electron LimitedInventors: Asao Yamashita, Merritt Funk, Daniel J. Prager, Lee Chen, Radha Sundararajan
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Patent number: 7906032Abstract: A method of conditioning a processing chamber for a production process includes performing a conditioning step at a conditioning process recipe substantially different than a process recipe of the production process, and performing a warm-up process at a warm-up process recipe substantially the same as the process recipe of the production process. The method can be performed after a wet-cleaning process has been performed. The conditioning procedure can allow the maintenance time to be decreased and can cause the etched features to be more accurate.Type: GrantFiled: March 31, 2006Date of Patent: March 15, 2011Assignee: Tokyo Electron LimitedInventor: Asao Yamashita
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Patent number: 7899637Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.Type: GrantFiled: June 13, 2007Date of Patent: March 1, 2011Assignee: Tokyo Electron LimitedInventors: Asao Yamashita, Merritt Funk, Daniel Prager, Lee Chen, Radha Sundararajan
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Patent number: 7894927Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.Type: GrantFiled: August 6, 2008Date of Patent: February 22, 2011Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee
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Patent number: 7877161Abstract: A processing system and method for chemical oxide removal (COR) is presented, wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.Type: GrantFiled: December 17, 2003Date of Patent: January 25, 2011Assignee: Tokyo Electron LimitedInventors: Masayuki Tomoyasu, Merritt Lane Funk, Kevin Augustine Pinto, Masaya Odagiri, Lemuel Chen, Asao Yamashita, Akira Iwami, Hiroyuki Takahashi
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Publication number: 20100214545Abstract: The invention can provide apparatus and methods of creating metal gate structures on wafers in real-time using Lithography-Etch-Lithography-Etch (LELE) processing sequence. Real-time data and/or historical data associated with LELE processing sequences can be fed forward and/or fed back as fixed variables or constrained variables in internal-Integrated-Metrology modules (i-IMM) to improve the accuracy of the metal gate structures.Type: ApplicationFiled: February 24, 2009Publication date: August 26, 2010Applicant: Tokyo Electron LimitedInventors: Merritt Funk, Daniel J. Prager, Asao Yamashita, Radha Sundararajan
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Patent number: 7763404Abstract: The present invention provides methods and system for improving the accuracy of measurements made using optical metrology. The present invention relates to methods and systems for changing the optical properties of tunable resists that can be used in the production of electronic devices such as integrated circuits. Further, the invention provides methods and systems for using a modifiable resist layer that provides a first set of optical properties before exposure and a second set of optical properties after exposure.Type: GrantFiled: September 26, 2006Date of Patent: July 27, 2010Assignee: Tokyo Electron LimitedInventors: James E. Willis, Manuel Perez, Asao Yamashita
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Patent number: 7765077Abstract: The invention can provide a method of processing a substrate using Spacer-Optimization (S-O) processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures. In addition, the S-O processing sequences can include one or more deposition procedures, one or more partial-etch procedures, one or more chemical oxide removal (COR)-etch procedures, one or more optimization procedures, one or more evaluation procedures, and/or one or more verification procedures.Type: GrantFiled: September 21, 2007Date of Patent: July 27, 2010Assignee: Tokyo Electron LimitedInventors: Asao Yamashita, Merritt Funk, Daniel J. Prager, Lee Chen, Radha Sundaranajan
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Patent number: 7713758Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.Type: GrantFiled: June 13, 2007Date of Patent: May 11, 2010Assignee: Tokyo Electon LimitedInventors: Asao Yamashita, Merritt Funk, Daniel Prager, Lee Chen, Radha Sundararajan
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Publication number: 20100036514Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.Type: ApplicationFiled: August 6, 2008Publication date: February 11, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee