Patents by Inventor Asao Yamashita

Asao Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060006136
    Abstract: A processing system and method for chemically treating a TERA layer on a substrate. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate. In one embodiment, the system for processing a TERA layer includes a plasma-enhanced chemical vapor deposition (PECVD) system for depositing the TERA layer on the substrate, an etching system for creating features in the TERA layer, and a processing subsystem for reducing the size of the features in the TERA layer.
    Type: Application
    Filed: July 6, 2004
    Publication date: January 12, 2006
    Applicant: Tokyo Electron Limited
    Inventors: Aelan Mosden, Asao Yamashita
  • Publication number: 20050227494
    Abstract: A method and system for trimming a feature on a substrate is described. During a chemical treatment of the substrate, the substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. An inert gas is also introduced, and the flow rate of the inert gas is selected in order to affect a target trim amount during the trimming of the feature.
    Type: Application
    Filed: March 30, 2004
    Publication date: October 13, 2005
    Applicant: Tokyo Electron Limited
    Inventors: Fumihiko Higuchi, Hiroyuki Takahashi, Akiteru Ko, Hongyu Yue, Asao Yamashita, Hiromitsu Kambara
  • Publication number: 20050221619
    Abstract: A system and method for transferring a pattern from an overlying layer into an underlying layer, while laterally trimming a feature present within the pattern is described. The pattern transfer is performed using an etch process according to a process recipe, wherein at least one variable parameter within the process recipe is adjusted given a target trim amount. The adjustment of the variable parameter is achieved using a process model established for relating trim amount data with the variable parameter.
    Type: Application
    Filed: April 12, 2005
    Publication date: October 6, 2005
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hongyu Yue, Asao Yamashita
  • Publication number: 20050106868
    Abstract: An etching method for plasma etching a polysilicon film layer on a gate oxide film formed on a silicon substrate by introducing a processing gas into an airtight processing chamber comprises a main etching step for etching, by applying high frequency powers to the upper and the lower electrode, the polysilicon film in a depth direction of openings of a mask pattern serving as a mask, and an overetching step for removing, after the main etching step, residual parts of the polysilicon film, wherein in the middle of the main etching step, the high frequency power applied to the upper electrode is lowered down to a specific power level or lower, and the polysilicon film is etched until a part of the gate oxide film is exposed. Anisotropy in the profile can be improved while enhancing the selectivity of etching, and total etching rate can be prevented from being lowered.
    Type: Application
    Filed: January 31, 2003
    Publication date: May 19, 2005
    Inventors: Asao Yamashita, Fumihiko Higuchi, Takashi Enomoto
  • Patent number: 6893975
    Abstract: A system and method for transferring a pattern from an overlying layer into an underlying layer, while laterally trimming a feature present within the pattern is described. The pattern transfer is performed using an etch process according to a process recipe, wherein at least one variable parameter within the process recipe is adjusted given a target trim amount. The adjustment of the variable parameter is achieved using a process model established for relating trim amount data with the variable parameter.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: May 17, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Hongyu Yue, Asao Yamashita
  • Publication number: 20050045588
    Abstract: A tungsten silicide layer (104) is etched by plasma etching using Cl2+O2 gas as etching gas. When etching of the tungsten silicide layer (104) is ended substantially, etching gas is switched to Cl2+O2+NF3 and over etching is performed by plasma etching. Etching process is ended under a state where a polysilicon layer (103) formed beneath the tungsten silicide layer (104) is slightly etched uniformly. Residual quantity of the polysilicon layer (103) can be made uniform as compared with prior art and a high quality semiconductor device can be fabricated stably.
    Type: Application
    Filed: February 27, 2002
    Publication date: March 3, 2005
    Inventors: Akiteru Koh, Toshihiro Miura, Takayuki Fukasawa, Akitaka Shimizu, Masato Kushibiki, Asao Yamashita, Fumihiko Higuchi
  • Publication number: 20040185583
    Abstract: A processing system and method for chemical oxide removal (COR) is presented, wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.
    Type: Application
    Filed: December 17, 2003
    Publication date: September 23, 2004
    Applicant: Tokyo Electron Limited
    Inventors: Masayuki Tomoyasu, Merritt Lane Funk, Kevin Augustine Pinto, Masaya Odagiri, Lemuel Chen, Asao Yamashita, Akira Iwami, Hiroyuki Takahashi
  • Publication number: 20040035365
    Abstract: An apparatus, which performs a plasma process on a target substrate by using plasma, includes first and second electrodes in a process chamber to oppose each other. An RF field, which turns a process gas into plasma by excitation, is formed between the first and second electrodes. An RF power supply, which supplies RF power, is connected to the first or second electrode through a matching circuit. The matching circuit automatically performs input impedance matching relative to the RF power. A variable impedance setting section is connected to a predetermined member, which is electrically coupled with the plasma, through an interconnection. The impedance setting section sets a backward-direction impedance against an RF component input to the predetermined member from the plasma. A controller supplies a control signal concerning a preset value of the backward-direction impedance to the impedance setting section.
    Type: Application
    Filed: July 10, 2003
    Publication date: February 26, 2004
    Inventors: Yohei Yamazawa, Manabu Iwata, Chishio Koshimizu, Fumihiko Higuchi, Akitaka Shimizu, Asao Yamashita, Nobuhiro Iwama, Tsutomu Higashiura, Dongsheng Zhang, Michiko Nakaya, Norikazu Murakami