Patents by Inventor Asao Yamashita
Asao Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100036518Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.Type: ApplicationFiled: August 6, 2008Publication date: February 11, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee
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Publication number: 20090242513Abstract: The invention provides a method of processing a substrate using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more masking layer creation procedures, one or more pre-processing measurement procedures, one or more Partial-Etch (P-E) procedures, one or more Final-Etch (F-E) procedures, and one or more post-processing measurement procedures.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Merritt Funk, Radha Sundararajan, Hyung Joo Lee, Daniel Prager, Asao Yamashita
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Patent number: 7527016Abstract: An apparatus, which performs a plasma process on a target substrate by using plasma, includes first and second electrodes in a process chamber to oppose each other. An RF field, which turns a process gas into plasma by excitation, is formed between the first and second electrodes. An RF power supply, which supplies RF power, is connected to the first or second electrode through a matching circuit. The matching circuit automatically performs input impedance matching relative to the RF power. A variable impedance setting section is connected to a predetermined member, which is electrically coupled with the plasma, through an interconnection. The impedance setting section sets a backward-direction impedance against an RF component input to the predetermined member from the plasma. A controller supplies a control signal concerning a preset value of the backward-direction impedance to the impedance setting section.Type: GrantFiled: July 10, 2003Date of Patent: May 5, 2009Assignee: Tokyo Electron LimitedInventors: Yohei Yamazawa, Manabu Iwata, Chishio Koshimizu, Fumihiko Higuchi, Akitaka Shimizu, Asao Yamashita, Nobuhiro Iwama, Tsutomu Higashiura, Dongsheng Zhang, Michiko Nakaya, Norikazu Murakami
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Publication number: 20090082983Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.Type: ApplicationFiled: September 21, 2007Publication date: March 26, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Asao Yamashita, Merritt Funk, Daniel J. Prager, Lee Chen, Radha Sundararajan
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Publication number: 20090081815Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.Type: ApplicationFiled: September 21, 2007Publication date: March 26, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Asao Yamashita, Merritt Funk, Daniel J. Prager, Lee Chen, Radha Sundararajan
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Publication number: 20080311688Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.Type: ApplicationFiled: June 13, 2007Publication date: December 18, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Asao Yamashita, Merritt Funk, Daniel Prager, Radha Sundararajan, Lee Chen
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Publication number: 20080311687Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.Type: ApplicationFiled: June 13, 2007Publication date: December 18, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Asao Yamashita, Merritt Funk, Daniel Prager, Lee Chen, Radha Sundararajan
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Publication number: 20080217294Abstract: A method of etching a hafnium containing layer includes disposing a substrate having the hafnium containing layer in a plasma processing system, wherein a mask layer defining a pattern therein overlies the hafnium containing layer. A process gas including a HBr gas is introduced to the plasma processing system, and a plasma is formed from the process gas in the plasma processing system. The hafnium containing layer is exposed to the plasma in order to treat the hafnium containing layer. The hafnium containing layer is then wet etched using a dilute HF wet etch process.Type: ApplicationFiled: March 9, 2007Publication date: September 11, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Akiteru Ko, Takashi Enomoto, Asao Yamashita
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Publication number: 20080076045Abstract: The present invention provides methods and system for improving the accuracy of measurements made using optical metrology. The present invention relates to methods and systems for changing the optical properties of tunable resists that can be used in the production of electronic devices such as integrated circuits. Further, the invention provides methods and systems for using a modifiable resist layer that provides a first set of optical properties before exposure and a second set of optical properties after exposure.Type: ApplicationFiled: September 26, 2006Publication date: March 27, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: James E. Willis, Manuel Perez, Asao Yamashita
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Patent number: 7328418Abstract: This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.Type: GrantFiled: February 1, 2005Date of Patent: February 5, 2008Assignee: Tokyo Electron LimitedInventors: Asao Yamashita, Merritt Funk, Daniel Prager
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Patent number: 7292906Abstract: A processing method of processing a substrate is presented that includes: receiving pre-process data, wherein the pre-process data comprises a desired process result and actual measured data for the substrate; determining a required process result, wherein the required process result comprises the difference between the desired process result and the actual measured data; creating a new process recipe by modifying a nominal recipe obtained from a processing tool using at least one of a static recipe and a formula model, wherein the new process recipe provides a new process result that is approximately equal to the required process result; and sending the new process recipe to the processing tool and the substrate.Type: GrantFiled: July 14, 2004Date of Patent: November 6, 2007Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Kevin Augustine Pinto, Asao Yamashita, Wesley Natzle
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Publication number: 20070238199Abstract: A method of conditioning a processing chamber for a production process includes performing a conditioning step at a conditioning process recipe substantially different than a process recipe of the production process, and performing a warm-up process at a warm-up process recipe substantially the same as the process recipe of the production process. The method can be performed after a wet-cleaning process has been performed. The conditioning procedure can allow the maintenance time to be decreased and can cause the etched features to be more accurate.Type: ApplicationFiled: March 31, 2006Publication date: October 11, 2007Applicant: TOKYO ELECTRON LIMITEDInventor: Asao Yamashita
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Publication number: 20070236148Abstract: An apparatus, which performs a plasma process on a target substrate by using plasma, includes first and second electrodes in a process chamber to oppose each other. An RF field, which turns a process gas into plasma by excitation, is formed between the first and second electrodes. An RF power supply, which supplies RF power, is connected to the first or second electrode through a matching circuit. The matching circuit automatically performs input impedance matching relative to the RF power. A variable impedance setting section is connected to a predetermined member, which is electrically coupled with the plasma, through an interconnection. The impedance setting section sets a backward-direction impedance against an RF component input to the predetermined member from the plasma. A controller supplies a control signal concerning a preset value of the backward-direction impedance to the impedance setting section.Type: ApplicationFiled: May 31, 2007Publication date: October 11, 2007Inventors: Yohei Yamazawa, Manabu Iwata, Chishio Koshimizu, Fumihiko Higuchi, Akitaka Shimizu, Asao Yamashita, Nobuhiro Iwama, Tsutomu Higashiura, DongSheng Zhang, Michiko Nakaya, Norikazu Murakami
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Patent number: 7209798Abstract: This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.Type: GrantFiled: September 20, 2004Date of Patent: April 24, 2007Assignee: Tokyo Electron LimitedInventors: Asao Yamashita, Merritt Lane Funk, Daniel Prager
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Patent number: 7192532Abstract: A tungsten silicide layer (104) is etched by plasma etching using Cl2+O2 gas as etching gas. When etching of the tungsten silicide layer (104) is ended substantially, etching gas is switched to Cl2+O2+NF3 and over etching is performed by plasma etching. Etching process is ended under a state where a polysilicon layer (103) formed beneath the tungsten silicide layer (104) is slightly etched uniformly. Residual quantity of the polysilicon layer (103) can be made uniform as compared with prior art and a high quality semiconductor device can be fabricated stably.Type: GrantFiled: February 27, 2002Date of Patent: March 20, 2007Assignee: Tokyo Electron LimitedInventors: Akiteru Koh, Toshihiro Miura, Takayuki Fukasawa, Akitaka Shimizu, Masato Kushibiki, Asao Yamashita, Fumihiko Higuchi
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Publication number: 20060254716Abstract: A processing system and method for chemically treating a TERA layer on a substrate. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate. In one embodiment, the system for processing a TERA layer includes a plasma-enhanced chemical vapor deposition (PECVD) system for depositing the TERA layer on the substrate, an etching system for creating features in the TERA layer, and a processing subsystem for reducing the size of the features in the TERA layer.Type: ApplicationFiled: July 14, 2006Publication date: November 16, 2006Applicant: Tokyo Electron LimitedInventors: Aelan Mosden, Asao Yamashita
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Publication number: 20060195218Abstract: This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.Type: ApplicationFiled: February 1, 2005Publication date: August 31, 2006Applicant: Tokyo Electron LimitedInventors: Asao Yamashita, Merritt Funk, Daniel Prager
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Patent number: 7097779Abstract: A processing system and method for chemically treating a TERA layer on a substrate. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate. In one embodiment, the system for processing a TERA layer includes a plasma-enhanced chemical vapor deposition (PECVD) system for depositing the TERA layer on the substrate, an etching system for creating features in the TERA layer, and a processing subsystem for reducing the size of the features in the TERA layer.Type: GrantFiled: July 6, 2004Date of Patent: August 29, 2006Assignee: Tokyo Electron LimitedInventors: Aelan Mosden, Asao Yamashita
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Publication number: 20060064193Abstract: This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.Type: ApplicationFiled: September 20, 2004Publication date: March 23, 2006Applicant: Tokyo Electron LimitedInventors: Asao Yamashita, Merritt Funk, Daniel Prager
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Publication number: 20060015206Abstract: A dual chamber apparatus including a first chamber and a second chamber which is configured to be coupled to the first chamber at an interface. Each of the first chamber and the second chamber has a transfer opening located at the interface. An insulating plate is located on one of the first chamber and the second chamber at the interface and is configured to have a low thermal conductivity such that the first chamber and the second chamber can be independently controlled at different temperatures when the first chamber and the second chamber are coupled together. Additionally, the apparatus may include an alignment device and/or a fastening device for fastening the first chamber to the second chamber. In embodiments, the insulating plate may be constructed of Teflon. Further, the first chamber may be a chemical oxide removal treatment chamber and the second chamber may be a heat treatment chamber.Type: ApplicationFiled: July 14, 2004Publication date: January 19, 2006Applicants: Tokyo Electron Limited, International Business Machines CorporationInventors: Merritt Funk, Kevin Pinto, Asao Yamashita, Wesley Natzle