Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming at least one magnetic tunnel junction (MTJ) stack on top of a supporting structure; forming a conformal liner surrounding a sidewall of the MTJ stack; forming a first dielectric layer surrounding the conformal liner; selectively forming a metal oxide layer on top of the conformal liner and the first dielectric layer, the metal oxide layer having at least a first opening that exposes a top surface of the MTJ stack; and forming a top contact contacting the top surface of the MTJ stack through the first opening in the metal oxide layer. An MRAM structure formed thereby is also provided.

Abstract: A semiconductor device includes a bottom electrode contact disposed over one or more of a plurality of conductive lines, magnetoresistive random access memory (MRAM) pillars constructed over the bottom electrode contact, an encapsulation layer section disposed between a pair of the MRAM pillars such that an aspect ratio of a tight pitch gap between the pair of the MRAM pillars is reduced, and a dielectric disposed within the encapsulation layer section, wherein the dielectric fills an entirety of a space defined within the encapsulation layer section. The MRAM pillars have a generally rectangular-shaped or cone-shaped configuration and the encapsulation layer section has a generally U-shaped or V-shaped configuration.

Abstract: A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a semiconductor structure. The semiconductor structure may include an embedded magnetic random access memory (MRAM) array electrically connected between a bottom metal level and a top metal level. The MRAM array may include a first tier with first MRAM cells and first vias above the first MRAM cells, and a second tier with second MRAM cells and second vias below the second MRAM cells.

Abstract: An interconnect structure is provided. The interconnect structure includes first conducting lines and second conducting lines. The first conducting lines are formed of a first metallic material and include at least one individual first conducting line in contact with a first corresponding substrate conducting line. The second conducting lines are formed of a second metallic material and include at least one individual second conducting line between neighboring first conducting lines and in contact with a second corresponding substrate conducting line. The at least one individual second conducting line is separated from each of the neighboring first conducting lines by controlled distances.

Abstract: Embodiments of the invention include a subtractive top via as a bottom electrode contact for an embedded memory structure. Forming the bottom electrode contact includes depositing a conductive material on an underlayer and etching the conductive material to form an extended via and a conductive pad as an integral unit. The extended via extends from the conductive pad such that the extended via is adjacent to a memory structure, the extended via being formed as a first contact for the memory structure.

Abstract: A semiconductor component includes an insulative layer having a lowermost surface arranged on top of a bottom dielectric material. The semiconductor component further includes a first interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the first interconnect structure is arranged at a first height relative to the lowermost surface of the insulative layer. The semiconductor component further includes a pillar connected to the first interconnect structure and extending through the insulative layer. The semiconductor component further includes a second interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the second interconnect structure is arranged at a second height relative to the lowermost surface of the insulative layer. The second height is different than the first height.

Abstract: A high-density resistive random-access memory array with self-aligned bottom electrode contact includes a plurality of electrically conductive structures embedded in an interconnect dielectric material layer, a bottom electrode selectively grown over, and electrically connected to, each of the electrically conductive structures with the bottom electrode above an electrically conductive structure being separated from the bottom electrode above another electrically conductive structure by a first dielectric filling layer, the bottom electrode having a semi-circular shape. The array further includes a resistive random-access memory pillar disposed above the bottom electrode.

Abstract: A semiconductor structure may include a magnetic tunnel junction layer on top and in electrical contact with a microstud, a hard mask layer on top of the magnetic tunnel junction layer, and a liner positioned along vertical sidewalls of the magnetic tunnel junction layer and vertical sidewalls of the hard mask layer. A top surface of the liner may be below a top surface of the hard mask layer. The semiconductor structure may include a spacer on top of the liner. The liner may separate the spacer from the magnetic tunnel junction layer and the hard mask layer. The semiconductor structure may include a first metal layer below and in electrical contact with the microstud and a second metal layer above the hard mask layer. A bottom portion of the second metal layer may surround a top portion of the hard mask layer.

Abstract: A semiconductor device structure and a method for fabricating the same. The semiconductor device structure includes an embedded memory device and an electrode in contact with a top surface of the memory embedded device. A metal encapsulation layer is in contact with a top surface of the electrode and a portion of sidewalls of the electrode. The metal encapsulation layer comprises one or more materials that are chemical etch resistant and are conductive when oxidized. The method includes forming an insulating layer over a memory device and an electrode in contact with the memory device. Portions of the insulating layer are etched. The etching exposes a top surface and a portion of sidewalls of the electrode. A metal encapsulation layer is formed over and in contact with the top surface and the portion of sidewalls of the electrode.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

Abstract: Embodiments of present invention provide a resistor structure. The resistor structure includes a first layer of electrically insulating material; and a second layer of resistive material directly adjacent to the first layer, wherein thermal conductivity of the first layer is equal to or larger than 100 W/m/K. In one embodiment, the first layer of electrically insulating material has a band gap equal to or larger than 4 eV and is selected from a group consisting of aluminum-nitride (AlN), boron-nitride (BN), and diamond (C).

Abstract: A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.

Abstract: A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.

Abstract: A semiconductor device structure and a method for fabricating the same. The semiconductor device structure includes an embedded memory device and an electrode in contact with a top surface of the memory embedded device. A metal encapsulation layer is in contact with a top surface of the electrode and a portion of sidewalls of the electrode. The metal encapsulation layer comprises one or more materials that are chemical etch resistant and are conductive when oxidized. The method includes forming an insulating layer over a memory device and an electrode in contact with the memory device. Portions of the insulating layer are etched. The etching exposes a top surface and a portion of sidewalls of the electrode. A metal encapsulation layer is formed over and in contact with the top surface and the portion of sidewalls of the electrode.

Abstract: A semiconductor substrate has a metal via in the substrate, and has, on the substrate, a metal line that is less than 8 nanometers (nm) wide and at least 20 nm tall. A method for making a semiconductor structure includes forming a metal via in a substrate; forming a mandrel atop and offset from the via; depositing a metal-containing liner onto the mandrel; exposing the top of the mandrel by anisotropically etching the liner, thereby defining a separate portion of the liner at each side of the mandrel; and growing a metal line on each portion of the liner.

Abstract: A memory device is provided. The memory device includes a memory stack on a first dielectric layer, and a sidewall spacer on the memory stack. The memory device further includes a conductive cap on the sidewall spacer and the memory stack and an upper metal line on the conductive cap and the sidewall spacer, wherein the upper metal line wraps around the conductive cap, sidewall spacer, and memory stack.

Abstract: A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

Abstract: A metallic hardmask is formed having a selected stress designed to create a selected amount of positive wafer bow. In preferred embodiments, metallic hardmask is disposed on a memory pillar layer over a wafer substrate. A set of memory pillars using the metal hardmask. Because of the positive wafer bow, the patterned set of memory pillars at both the edges and the central portion of the wafer substrate are aligned with a respective contact for a memory device. A positive wafer bow is defined as a bowed wafer substrate where a central portion of a patterned side of the wafer substrate is lower than edges of the wafer substrate.