Abstract: A method for making a semiconductor apparatus includes forming a first bottom interconnect in a device area of a first dielectric layer; fabricating a device on top of the first bottom interconnect; capping the device with a first interlayer dielectric; exposing a logic area of the first dielectric layer that is adjacent to the device area by removing a portion of the first interlayer dielectric from the first dielectric layer while leaving another portion of the first interlayer dielectric that caps the device; and forming a second bottom interconnect in the logic area of the first dielectric layer. By forming the second bottom interconnect after the device fabrication and capping, damage to the device and to the second bottom interconnect is avoided.

Abstract: An anti-fuse device having enhanced programming efficiency is provided. The anti-fuse device includes via contact structures that have different critical dimensions located between a first electrode and a second electrode. Notably, a first via contact structure having a first critical dimension is provided between a pair of second via contact structures having a second critical dimension that is greater than the first critical dimension. When a voltage is applied to the device, dielectric breakdown will occur first through the first via contact structure having the first critical dimension.

Abstract: Controlled IBE techniques for MRAM stack patterning are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cells using IBE landing on the dielectric while dynamically adjusting an etch time to compensate for variations in a thickness of the MRAM stack, wherein each of the memory cells includes a bottom electrode, an MTJ, and a top electrode; removing foot flares from the bottom electrode of the memory cells which are created during the patterning of the MRAM stack; removing residue from sidewalls of the memory cells which includes metal redeposited during the patterning of the MRAM stack and during the removing of the foot flares; and covering the memory cells in a dielectric encapsulant. An MRAM device is also provided.

Abstract: A method includes forming a first metallization layer containing a first metal-containing line and a second metal-containing line disposed in a first interlevel dielectric layer. The first metal-containing line includes a first conductive metal and the second metal-containing line includes a second conductive metal. The first metal-containing line and the second metal-containing line are recessed to below a top surface of the interlevel dielectric layer. A metal-containing cap protection layer is deposited in a recessed portion of the first metal-containing line and the second metal-containing line. The metal-containing cap protection layer includes a third conductive metal which is different than the first conductive metal and the second conductive metal.

Abstract: Techniques for self-aligned top via formation at line ends are provided. In one aspect, a method of forming self-aligned vias at line ends includes: patterning (even/odd) metal lines including using a (first/second) hardmask; cutting the hardmask and a select metal line, even or odd, using a cut mask having a window that exposes the hardmask over a cut region of the select metal line; enlarging the window to expose the hardmask on either side of the cut region; selectively etching the hardmask using the enlarged window to form a T-shaped cavity within the cut region; filling the T-shaped cavity with a gap fill dielectric; removing the hardmask; and recessing the metal lines, wherein the gap fill dielectric overhangs portions of the select metal line that, by the recessing, form the self-aligned vias at ends of the metal lines. A structure is also provided.

Abstract: A semiconductor device includes a base structure of an embedded memory device including a bottom electrode contact (BEC) landing pad within a memory area of the embedded memory device and a first metallization level having at least a first conductive line within a logic area of the embedded memory device, a cap layer disposed on the base structure, a BEC disposed through the cap layer on the BEC landing pad, a memory pillar disposed on the BEC and the cap layer, encapsulation layers encapsulating the memory pillar to protect the memory stack, and a second metallization level including a second conductive line surrounding the top electrode, a via disposed on the first conductive line such that the second via is below the top electrode, and a third conductive line disposed on the via to enable the memory pillar to be fitted between the first and second metallization levels.

Abstract: A method of forming a self-aligned top via is provided. The method includes forming a metallization layer on a substrate, and forming a hardmask layer on the metallization layer. The method further includes forming a pair of adjacent parallel mandrels on the hardmask layer with sidewall spacers on opposite sides of each mandrel. The method further includes forming a planarization layer on the exposed portions of the hardmask layer, mandrels, and sidewall spacers, and forming an opening in the planarization layer aligned between the adjacent parallel mandrels. The method further includes forming a spacer layer in the opening, and removing portions of the spacer layer to form a pair of spacer plugs between sections of the sidewall spacers.

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

Abstract: A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer; and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.

Abstract: A method includes forming a plurality of elongated dielectric members on a semiconductor substrate. The elongated dielectric members each extend vertically from the semiconductor substrate and define opposed vertical walls. The method further includes forming opposed spacer walls on the vertical walls of the elongated dielectric members. Adjacent spacer walls of longitudinally adjacent elongated dielectric members define first trenches therebetween. The method also includes depositing a first metal material within the first trenches to form a first set of first metal lines, removing the elongated dielectric members to define second trenches between the opposed spacer wails on the opposed vertical wails of each elongated dielectric member, and depositing a second metal material within the second trenches to form a second set of second metal lines. The first and second metal lines of the first and second sets are disposed in alternating arrangement.

Abstract: Techniques for preserving the underlying dielectric layer during MRAM device formation are provided. In one aspect, a method of forming an MRAM device includes: depositing a first dielectric cap layer onto a substrate over logic and memory areas of the substrate; depositing a sacrificial metal layer onto the first dielectric cap layer; patterning the sacrificial metal layer, wherein the patterned sacrificial metal layer is present over the first dielectric cap layer in at least the logic area; depositing a second dielectric cap layer onto the first dielectric cap layer; forming an MRAM stack on the second dielectric cap layer; patterning the MRAM stack using ion beam etching into at least one memory cell, wherein the patterned sacrificial metal layer protects the first dielectric cap layer in the logic area; and removing the patterned sacrificial metal layer. An MRAM device is also provided.

Abstract: Techniques for integrating an embedded MRAM device with a BEOL interconnect structure are provided. In one aspect, a method of forming an embedded MRAM device includes: depositing a cap layer onto a substrate; forming a metal line and metal pad on the cap layer; patterning the metal line to form first top vias, and the metal pad to form a second top via; depositing a dielectric material onto the substrate surrounding the first/second top vias; recessing the second top via to form a bottom contact via self-aligned to the metal pad which serves as a bottom contact; forming an MRAM cell over the bottom contact via; and forming first/second top contacts in contact with the first top vias/the MRAM cell. An embedded MRAM device is also provided.

Abstract: Form a metallized layer at a top surface of a semiconductor wafer. The metallized layer includes a bottom contact and a dielectric barrier surrounding the bottom contact. Deposit a memory stack layer onto the metallized layer. The memory stack layer forms a first overspill on a bevel of the wafer. Remove the first overspill from the bevel using a first high-angle ion beam during a cleanup etch.

Abstract: Techniques for forming barrierless contacts filled with Co are provided. In one aspect, a method for forming barrierless contacts includes: forming bottom metal contacts in a first ILD; depositing a second ILD on the bottom metal contacts; forming contact vias in the second ILD landing on the bottom metal contacts; selectively forming a liner on a top surface of the second ILD and on the second ILD along sidewalls of the contact vias; filling the contact vias with a metal; and removing an excess of the metal to form the barrierless contacts whereby metal-to-metal contact is present between the barrierless contacts and the bottom metal contacts. A contact structure is also provided.

Abstract: An anti-fuse device having enhanced programming efficiency is provided. The anti-fuse device includes via contact structures that have different critical dimensions located between a first electrode and a second electrode. Notably, a first via contact structure having a first critical dimension is provided between a pair of second via contact structures having a second critical dimension that is greater than the first critical dimension. When a voltage is applied to the device, dielectric breakdown will occur first through the first via contact structure having the first critical dimension.

Abstract: Re-depositing of metal-containing particles of an embedded electrically conductive structure onto sidewalls of an overlying metal-containing structure is alleviated in the present application by providing a pedestal structure between the embedded electrically conductive structure and the metal-containing structure, wherein the pedestal structure has a flared sidewall that extends beyond a perimeter of the embedded electrically conductive structure. Such a pedestal structure (which can be referred to herein as a footing flare pedestal structure) mitigates, and in some embodiments, entirely eliminates, the exposure of the embedded electrically conductive structure during the patterning of metal-containing layers formed atop the embedded electrically conductive structure.

Abstract: Form a metallized layer at a top surface of a semiconductor wafer. The metallized layer includes a bottom contact and a dielectric barrier surrounding the bottom contact. Deposit a memory stack layer onto the metallized layer. The memory stack layer forms a first overspill on a bevel of the wafer. Remove the first overspill from the bevel using a first high-angle ion beam during a cleanup etch.

Abstract: A method for forming one or more self-aligned contacts on a semiconductor device includes applying a protective layer on an oxide surface above a source and drain of the semiconductor device. The protective layer covers a top surface of the oxide surface selective to nitride above a gate contact pillar. A sacrificial layer is applied to the nitride surface. The sacrificial layer is deposited only on the nitride surface that is selective to the oxide layer coated with the protective layer. The protective layer is removed from the oxide surface and source/drain contact holes are etched in the oxide surface to form self-aligned contacts on the semiconductor device.

Abstract: Provided are embodiments for a semiconductor device that includes a bottom contact; a multi-layer bottom electrode formed over the bottom contact; a magnetic tunnel junction stack formed over the multi-layer bottom electrode; and a top electrode formed over the magnetic tunnel junction stack. Also provided are embodiments for forming the semiconductor device described herein.

Abstract: A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.