Abstract: A method of forming polycrystalline silicon with ultra-small grain sizes employs a differential heating of the upper and lower sides of the substrate of a CVD apparatus, in which the lower side of the substrate receives considerably more power than the upper side, preferable more than 75% of the power; and in which the substrate is maintained during deposition at a temperature more than 50° C. above the 550° C. crystallization temperature of silicon.

Abstract: A compound that includes at least Si, N and C in any combination, such as compounds of formula (R—NH)4-nSiXn wherein R is an alkyl group (which may be the same or different), n is 1, 2 or 3, and X is H or halogen (such as, e.g., bis-tertiary butyl amino silane (BTBAS)), may be mixed with silane or a silane derivative to produce a film. A polysilicon silicon film may be grown by mixing silane (SiH4) or a silane derviative and a compound including Si, N and C, such as BTBAS. Films controllably doped with carbon and/or nitrogen (such as layered films) may be grown by varying the reagents and conditions.

Abstract: Stress level of a nitride film is adjusted as a function of two or more of the following: identity of a starting material precursor used to make the nitride film; identity of a nitrogen-containing precursor with which is treated the starting material precursor; ratio of the starting material precursor to the nitrogen-containing precursor; a set of CVD conditions under which the film is grown; and/or a thickness to which the film is grown. A rapid thermal chemical vapor deposition (RTCVD) film produced by reacting a compound containing silicon, nitrogen and carbon (such as bis-tertiary butyl amino silane (BTBAS)) with NH3 can provide advantageous properties, such as high stress and excellent performance in an etch-stop application. An ammonia-treated BTBAS film is particularly excellent in providing a high-stress property, and further having maintainability of that high-stress property over repeated annealing.

Abstract: A semiconductor device structure includes a substrate, a dielectric layer disposed on the substrate, first and second stacks disposed on the dielectric layer. The first stack includes a first silicon layer disposed on the dielectric layer, a silicon germanium layer disposed on the first silicon layer, a second silicon layer disposed on the silicon germanium layer, and a third silicon layer disposed on the second silicon layer. The second stack includes a first silicon layer disposed on the dielectric layer, and a second silicon layer disposed on the first silicon layer. Alternatively, the silicon germanium layer includes Boron.

Abstract: A semiconductor device structure includes a substrate, a dielectric layer disposed on the substrate, first and second stacks disposed on the dielectric layer. The first stack includes a first silicon layer disposed on the dielectric layer, a silicon germanium layer disposed on the first silicon layer, a second silicon layer disposed on the silicon germanium layer, and a third silicon layer disposed on the second silicon layer. The second stack includes a first silicon layer disposed on the dielectric layer, and a second silicon layer disposed on the first silicon layer. Alternatively, the silicon germanium layer includes Boron.

Abstract: A method is provided for reducing the microloading effect in a CVD process for depositing a film on a substrate. This method is particularly useful in a single-wafer CVD reactor. The microloading effect is reduced by identifying a growth-rate-limiting reactant; calculating a dilution factor (the ratio of the gas flow rate of the growth-rate-limiting reactant to the total gas flow rate in the reactor); and adjusting the film growth rate and/or the dilution factor to satisfy a numerical criterion for reducing the microloading effect. The criterion is satisfied when the film growth rate is reduced, or the dilution factor is increased, so that the dilution factor is equal to or greater than a quantity which includes the film growth rate as a factor. The film growth rate and dilution factor may be adjusted independently. The gap between the showerhead and the substrate in the CVD reactor may be adjusted to satisfy the numerical criterion.

Abstract: A compact resistor is formed in an integrated circuit using many of the same steps as are employed in forming a trench capacitor for a DRAM cell; in particular depositing a layer of heavily doped germanium in the trench interior after the step of doping the substrate to form the bottom plate for the capacitor, depositing polysilicon having the required resistivity in the trench then removing the germanium and leaving only enough to form an ohmic contact in the trench bottom.

Abstract: A method is provided for reducing the microloading effect in a CVD process for depositing a film on a substrate. This method is particularly useful in a single-wafer CVD reactor. The microloading effect is reduced by identifying a growth-rate-limiting reactant; calculating a dilution factor (the ratio of the gas flow rate of the growth-rate-limiting reactant to the total gas flow rate in the reactor); and adjusting the film growth rate and/or the dilution factor to satisfy a numerical criterion for reducing the microloading effect. The criterion is satisfied when the film growth rate is reduced, or the dilution factor is increased, so that the dilution factor is equal to or greater than a quantity which includes the film growth rate as a factor. The film growth rate and dilution factor may be adjusted independently. The gap between the showerhead and the substrate in the CVD reactor may be adjusted to satisfy the numerical criterion.

Abstract: A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH)4−nSiXn, wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.

Abstract: A CVD process for the deposition of silicon oxide by reacting BTBAS with an ozone reactant gas comprising providing a semiconductor wafer substrate in a single wafer reactor, contacting said substrate with a gaseous mixture containing a bis-tertiary butyl aminosilane reactant and an ozone reactant at a pressure ranging from about 10 Torr to about 760 Torr, and, heating said mixture at a temperature ranging from about 400 to about 600° C., whereby said reactants are reacted to deposit said oxide as a film on said substrate.

Abstract: A method for removing surface oxide from polysilicon includes depositing a very thin layer of germanium (e.g. monolayers in thickness) over the polysilicon immediately before a subsequent polysilicon deposition step, and then heating the germanium-coated polysilicon in a vacuum to sublime (remove) volatile germanium oxide. This method is applied to formation of a trench capacitor, which uses either doped amorphous silicon or doped amorphous SiGe material in the formation of the electrodes.

Abstract: A disclosed process use low pressure chemical vapor deposition (LPCVD) of doped oxide film on a substrate. The process includes the steps of providing a substrate in an LPCVD reactor and flowing BTBAS and oxygen into the LPCVD reactor to react on the substrate to deposit an oxide film on the substrate. A doped precursor is flowed into the LPCVD reactor to dope the oxide film as it is deposited on the substrate. This process produces doped oxide film at a relatively low LPCVD reaction temperature.

Abstract: A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH)4−nSiXn, wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.

Abstract: A method of depositing a fluorinated borophosphosilicate glass (FBPSG) on a semiconductor device as either a final or interlayer dielectric film. Gaps having aspect ratios greater than 6:1 are filled with a substantially void-free FBPSG film at a temperature of about 480.degree. C. at sub-atmospheric pressures of about 200 Torr. Preferably, gaseous reactants used in the method comprise TEOS, FTES, TEPO and TEB with an ozone/oxygen mixture. Dopant concentrations of boron and phosphorus are sufficiently low such that surface crystallite defects and hygroscopicity are avoided. The as-deposited films at lower aspect ratio gaps are substantially void-free such that subsequent anneal of the film is not required. Films deposited into higher aspect ratio gaps are annealed at or below about 750.degree. C., well within the thermal budget for most DRAM, logic and merged logic-DRAM chips. The resultant FBPSG layer contains less than or equal to about 5.0 wt % boron, less than about 4.0 wt % phosphorus, and about 0.

Abstract: Filling of narrow and/or high aspect ratio gaps and trenches with silicate glass is accomplished at reduced temperatures and without reflow by etching the glass concurrently with thermal chemical vapor deposition of the glass such that the deposition rate will exceed the etching rate by a relatively small net deposition rate near the surface with the excess deposition rate increasing over the depth of the trench or gap. The as-deposited glass film is made dense and stable by carrying out the concurrent etch and deposition process at an elevated temperature but which is within the maximum temperature and heat budget which can be tolerated by structures formed by previously performed processes. Fluorine can be incorporated in the silicate glass film as a dopant in sufficient concentration to reduce dielectric constant of the film. Phosphorus and/or boron can be incorporated into the film, as well, and may enhance void-free filling of trenches and gaps.

Abstract: A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and etch steps having varying etch rate-to-deposition rate (etch/dep) ratios. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted before the opening to the gap is closed. The second step uses an etch/dep ratio greater than one to widen the gap. The second step is stopped before corners of the elements forming the gaps are exposed. These steps can be repeated until the aspect ratio of the gap is reduced so that void-free gap-fill is possible. The etch/dep ratio and duration of each step can be optimized for high throughput and high aspect ratio gap-fill capacity.

Abstract: A fluorinated phosphosilicate glass (FPSG) is produced in a plasma-enhanced chemical vapor deposition process (PECVD) in which the plasma source comprises conventional phosphosilicate glass-forming materials together with one or more fluorine gas-forming materials. The deposited fluorine-gas enhances the filling of gaps or voids with dielectric glass compositions by etching the top of the via holes or gaps during the filling operation. The present fluorine-doped phosphosilicate glass compositions are stable compared to conventional phosphosilicate glass compositions which are relatively unstable and unsatisfactory for use as gap-filling dielectric glass compositions.