Abstract: A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atomic percent of a first semiconductor material in the first semiconductor layer is equal to a substrate atomic percent of the substrate semiconductor material in the semiconductor substrate.

Abstract: Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.

Abstract: A method of making a semiconductor device includes forming a transistor structure having one of an embedded epitaxial stressed material in a source and drain region and a stressed channel and well, subjecting the transistor structure to plasma oxidation, and removing spacer material from the transistor structure.

Abstract: Trenches are formed in a silicon substrate by etching exposed portions of the silicon substrate. After covering areas on which deposition of Si:C containing material is to be prevented, selective epitaxy is performed in a single wafer chamber at a temperature from about 550° C. to about 600° C. employing a limited carrier gas flow, i.e., at a flow rate less than 12 standard liters per minute to deposit Si:C containing regions at a pattern-independent uniform deposition rate. The inventive selective epitaxy process for Si:C deposition provides a relatively high net deposition rate a high quality Si:C crystal in which the carbon atoms are incorporated into substitutional sites as verified by X-ray diffraction.

Abstract: Methods of fabricating a semiconductor structure with a non- epitaxial thin film disposed on a surface of a substrate of the semiconductor structure are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process.

Abstract: Methods of fabricating a semiconductor structure with a non-epitaxial thin film disposed on a surface of a substrate of the semiconductor structure; and semiconductor structures formed thereof are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process.

Abstract: Trenches are formed in a silicon substrate by etching exposed portions of the silicon substrate. After covering areas on which deposition of Si:C containing material is to be prevented, selective epitaxy is performed in a single wafer chamber at a temperature from about 550° C. to about 600° C. employing a limited carrier gas flow, i.e., at a flow rate less than 12 standard liters per minute to deposit Si:C containing regions at a pattern-independent uniform deposition rate. The inventive selective epitaxy process for Si:C deposition provides a relatively high net deposition rate a high quality Si:C crystal in which the carbon atoms are incorporated into substitutional sites as verified by X-ray diffraction.

Abstract: A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atom percent of the semiconductor material in the first semiconductor layer is equal to a certain atom percent of the semiconductor material in the semiconductor substrate.

Abstract: Methods for forming carbon silicon alloy (CSA) and structures thereof are disclosed. The method provides improvement in substitutionality and deposition rate of carbon in epitaxially grown carbon silicon alloy layers (i.e., substituted carbon in Si lattice). In one embodiment of the disclosed method, a carbon silicon alloy layer is epitaxially grown on a substrate at an intermediate temperature with a silicon precursor, a carbon (C) precursor in the presence of an etchant and a trace amount of germanium material (e.g., germane (GeH4)). The intermediate temperature increases the percentage of substitutional carbon in epitaxially grown CSA layer and avoids any tendency for silicon carbide to form. The presence of the trace amount of germanium material, of approximately less than 1% to approximately 5%, in the resulting epitaxial layer, has an effect of stabilizing and enhancing deposition/growth rate without compromising the tensile stress of CSA layer formed thereby.

Abstract: A method of forming at least one gate conductor of a complementary metal oxide semiconductor performs a chemical vapor deposition process of polysilicon over a surface where a polysilicon gate is to be located. This deposition can be performed through a mask to form gate structures directly, or a later patterning process can pattern the polysilicon into gate structures. During the chemical vapor deposition process, the method adds impurities in the chemical vapor deposition process to optimize the grain size of the polysilicon according to a number of different methods.

Abstract: Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.

Abstract: Methods of fabricating a semiconductor structure with a non-epitaxial thin film disposed on a surface of a substrate of the semiconductor structure; and semiconductor structures formed thereof are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process.

Abstract: A method of making a semiconductor device includes forming a transistor structure having one of an embedded epitaxial stressed material in a source and drain region and a stressed channel and well, subjecting the transistor structure to plasma oxidation, and removing spacer material from the transistor structure.

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.

Abstract: A dielectric element, and method of manufacturing the same, is disclosed for a semiconductor structure which comprises a substrate having a gate formed on a top surface of the substrate. The substrate and gate define a gap in a region between the gate and the substrate. A specified amount of dielectric on the substrate, at least a portion of which is in the gap, forms the dielectric element which substantially prevents unwanted electrical connectivity between the gate and the substrate.

Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.

Abstract: An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.

Abstract: Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.