Abstract: A voltage drive system is provided having a plurality of modulators and a plurality of cascaded switching circuits which collectively generate a single-phase output signal to a load. Each modulator receives a phase current error and has an adder which generates a modulated phase current error based on the phase current error and based on a signal having a phase. For each respective modulator, the phase of the respective signal is different. Each respective modulator changes a respective gate input when the respective modulated phase current error changes from being within a predetermined current range to being outside of the predetermined current range. Each respective switching circuit receives the respective gate input and generates a respective output terminal voltage based on the respective gate input. The change in the respective gate input effectively causes a switching event of the respective switching circuit.

Abstract: An apparatus and method for testing sense amplifier threshold voltages on an integrated circuit includes one or more sense amplifier modules each including a number of sense amplifier circuits, a voltage generator unit, and detection logic. The voltage generator unit may select a differential voltage to supply to at least some of the sense amplifier circuits, and each sense amplifier circuit may be configured to generate an output value that is dependent upon the applied differential voltage in response to receiving an enable signal. The detection logic may detect and capture an output value of each of the sense amplifier circuits. In one implementation, the voltage generator unit may iteratively select a different differential voltage in response to a control input. Accordingly, the detection logic may capture the output value of the sense amplifiers after each change in differential voltage.

Abstract: A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to select a particular SRAM cell in response to a selection input. An oscillator circuit such as a ring oscillator, for example, on the integrated circuit may be configured to oscillate at a frequency that is dependent upon a read current of a selected SRAM cell during operation in a first mode. A frequency determining circuit that is coupled to the oscillator circuit may be configured to output a value corresponding to the frequency of oscillation of the oscillator circuit.

Abstract: An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage onto a respective driver output line. Each drive detection unit may include a number of keeper circuits, each coupled to a separate output line and configured to retain a given voltage on the output line to which it is coupled. Each detection unit may also include a number of detection circuits coupled to detect the drive voltage on each of the output lines. In one implementation, the drive voltage appearing at the output line of each driver may be indicative of that the driver was able to overdrive the voltage being retained on the output line to which it is coupled by the respective keeper circuits.

Abstract: An apparatus and method for testing level shifter threshold voltages on an integrated circuit includes one or more level shifter modules each including a number of level shifter circuits. Each level shifter circuit may be coupled to a first and a second voltage supply. Each level shifter circuit may also receive an input signal that is referenced to the first voltage supply, and to generate an output signal that is referenced to the second voltage supply. In addition, each level shifter module may include detection logic that may detect an output value of each of the level shifter circuits. The control circuit may be configured to iteratively change the voltage output from one of the voltage supplies, and maintaining a voltage on the other voltage supply while the input signal is provided to the level shifter circuits. The detection logic may capture the output value upon each change in voltage.

Abstract: A high voltage inverter is provided which includes a plurality of k-level flying capacitor H bridge modules, k being greater than 2, each having a positive dc terminal, a negative dc terminal, and two ac terminals, a connecting unit for connecting said ac terminals of said plurality of k-level flying capacitor H bridge modules in series to form a cascading set of modules, and a dc source connected to an ac source and having a transformer, a rectifier rectifying an output voltage of said transformer, and a capacitor connected between the positive and negative dc terminals.

Abstract: A voltage drive system is provided having a plurality of modulators and a plurality of cascaded switching circuits which collectively generate a single-phase output signal to a load. Each modulator receives a phase current error and has an adder which generates a modulated phase current error based on the phase current error and based on a signal having a phase. For each respective modulator, the phase of the respective signal is different. Each respective modulator changes a respective gate input when the respective modulated phase current error changes from being within a predetermined current range to being outside of the predetermined current range. Each respective switching circuit receives the respective gate input and generates a respective output terminal voltage based on the respective gate input. The change in the respective gate input effectively causes a switching event of the respective switching circuit.

Abstract: A four pole, three-phase, NPC converter that produces virtually no common mode voltage. The low common mode voltage output is achieved by constraining the switch states of the NPC converter. A fourth pole and associated control balance the upper and lower DC link voltages. The converter may be an inverter or a rectifier.

Abstract: In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to the logic circuit. The logic circuit is configured to identify a first input of the plurality of inputs that is: (i) captured in error from a corresponding one of the plurality of outputs of the delay chain, and (ii) the corresponding one of the plurality of outputs of the delay chain is least delayed by the delay chain among the plurality of outputs that are captured in error. The plurality of clocked storage devices are configured to accumulate an indication of which of the plurality of outputs have been captured in error over a plurality of clock cycles of the first clock input.

Abstract: In one embodiment, an integrated circuit includes at least one digital leakage detector that includes digital circuitry configured to detect an approximation of a magnitude of the leakage current in transistors of the integrated circuit and configured to generate a digital output representing the approximated magnitude. In another embodiment, a leak detector includes leak circuits and clocked storage devices. Each leak circuit is configured to generate an output signal indicative of a different magnitude of leakage current in a transistor. The clocked storage devices are configured to capture a state representing the output signals of the leak circuits. In another embodiment, a method includes running a test for leakage current in a digital leakage detector, wherein a digital output of the digital leakage detector represents a magnitude of a leakage current being experienced by the integrated circuit during use; and outputting the digital output from the integrated circuit.

Abstract: A medium voltage power converter is provided that has an input transformer adapted to connect to a multi-phase power source, multiple low voltage drives each coupled to a respective set of secondary windings of the input transformer and operatively configured to provide a corresponding set of three-phase power outputs, and an output transformer. The output transformer has multiple input primary winding circuits each operatively coupled to the three-phase power outputs of a respective one of the drives, a plurality of output secondary winding circuits each disposed in relation to a respective input primary winding circuit, and a secondary winding connection arrangement in which each output secondary winding circuit has three secondary windings each of which is connected in series or in parallel with each other secondary winding of each other output secondary winding circuit to form a respective one of three phase-shifted outputs of the secondary winding connection arrangement.