Patents by Inventor Ashot Melik-Martirosian
Ashot Melik-Martirosian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10613781Abstract: A method populates a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit. A desired condition limit is identified, and a first parameter is computed as a function of a first memory operation to be performed on the memory block. The first parameter is included in a parameter set, and the memory block is cycled until the operating condition reaches the desired condition limit. After cycling, a second parameter is determined as a function of a second memory operation to be performed on the memory block, and the second parameter is included in the parameter set. The steps of cycling, and determining and the including the second parameter may be repeated until a desired number of cycles/parameters are reached. A retention bake may also be performed on the memory circuit, and a bit error rate resulting from a read operation verified.Type: GrantFiled: July 11, 2016Date of Patent: April 7, 2020Assignee: Western Digital Technologies, Inc.Inventor: Ashot Melik-Martirosian
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Patent number: 9977736Abstract: A method for managing memory operations in a storage device having a plurality of data blocks, the method including steps for determining a number of page reads for each of the plurality of data blocks and determining a dwell time for each of the plurality of data blocks. In certain aspects, the method further includes steps for associating the plurality of data blocks with a plurality of rank groups based on the number of page reads and the dwell time associated with each of the plurality of data blocks and selecting a data block, from among the plurality of data blocks, for memory reclamation based on the associated rank group and the selected data block. A storage system and computer-readable media are also provided.Type: GrantFiled: July 13, 2015Date of Patent: May 22, 2018Assignee: Western Digital Technologies, Inc.Inventor: Ashot Melik-Martirosian
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Patent number: 9805793Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.Type: GrantFiled: April 1, 2016Date of Patent: October 31, 2017Assignee: SanDisk Technologies LLCInventors: Bijesh Rajamohanan, Juan Saenz, Alvaro Padilla, Mohsen Purahmad, Ashot Melik-Martirosian
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Publication number: 20170287557Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Applicant: SanDisk Technologies Inc.Inventors: Bijesh Rajamohanan, Juan Saenz, Alvaro Padilla, Mohsen Purahmad, Ashot Melik-Martirosian
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Patent number: 9741768Abstract: A method is provided that includes forming a vertical bit line disposed in a first direction above a substrate, forming a multi-layer word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a memory cell including a nonvolatile memory material at an intersection of the vertical bit line and the multi-layer word line. The multi-layer word line includes a first conductive material layer and a second conductive material layer disposed above the first conductive material layer. The memory cell includes a working cell area encompassed by an intersection of the first conductive material layer and the nonvolatile memory material.Type: GrantFiled: March 31, 2016Date of Patent: August 22, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Ashot Melik-Martirosian, Juan Saenz
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Publication number: 20170010836Abstract: A method populates a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit. A desired condition limit is identified, and a first parameter is computed as a function of a first memory operation to be performed on the memory block. The first parameter is included in a parameter set, and the memory block is cycled until the operating condition reaches the desired condition limit. After cycling, a second parameter is determined as a function of a second memory operation to be performed on the memory block, and the second parameter is included in the parameter set. The steps of cycling, and determining and the including the second parameter may be repeated until a desired number of cycles/parameters are reached. A retention bake may also be performed on the memory circuit, and a bit error rate resulting from a read operation verified.Type: ApplicationFiled: July 11, 2016Publication date: January 12, 2017Inventor: Ashot MELIK-MARTIROSIAN
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Patent number: 9514823Abstract: A method applies a first set of consecutive pulses to flash memory cells in one or more flash memory devices to program the flash memory cells using a first pulse increment, a voltage of each consecutive pulse of the first set being incremented by the first pulse increment. On receiving an indication that the flash memory cells are partially programmed after the first set of consecutive pulses is applied, the first pulse increment is adjusted to an adjusted pulse increment based on a number of program/erase cycles associated with the flash memory cells. A second set of consecutive pulses to the flash memory cells is then applied using the adjusted pulse increment, a voltage of each consecutive pulse of the second set being incremented by the adjusted pulse increment.Type: GrantFiled: July 8, 2015Date of Patent: December 6, 2016Assignee: HGST Technologies Santa Ana, Inc.Inventor: Ashot Melik-Martirosian
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Patent number: 9389938Abstract: A method populates a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit. A desired condition limit is identified, and a first parameter is computed as a function of a first memory operation to be performed on the memory block. The first parameter is included in a parameter set, and the memory block is cycled until the operating condition reaches the desired condition limit. After cycling, a second parameter is determined as a function of a second memory operation to be performed on the memory block, and the second parameter is included in the parameter set. The steps of cycling, and determining and the including the second parameter may be repeated until a desired number of cycles/parameters are reached. A retention bake may also be performed on the memory circuit, and a bit error rate resulting from a read operation verified.Type: GrantFiled: April 14, 2014Date of Patent: July 12, 2016Assignee: HGST Technologies Santa Ana, Inc.Inventor: Ashot Melik-Martirosian
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Publication number: 20160179399Abstract: Systems and methods for garbage collection in a memory device are disclosed. The memory device includes a plurality of blocks that may be filled with data. In the event that the memory device needs to remove invalid data stored in the blocks, the memory device may perform a garbage collection process. To select the blocks for garbage collection, the memory device may examine both the number of invalid pages in the blocks and the health of the blocks (e.g., the program/erase cycles, erase speed, and program speed). Thus, the memory device may select the blocks for garbage collection that have the most invalid pages and are the healthiest. In this manner, the memory device may more evenly wear the blocks in the memory device.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Applicant: SanDisk Technologies Inc.Inventor: Ashot Melik-Martirosian
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Publication number: 20150317247Abstract: A method for managing memory operations in a storage device having a plurality of data blocks, the method including steps for determining a number of page reads for each of the plurality of data blocks and determining a dwell time for each of the plurality of data blocks. In certain aspects, the method further includes steps for associating the plurality of data blocks with a plurality of rank groups based on the number of page reads and the dwell time associated with each of the plurality of data blocks and selecting a data block, from among the plurality of data blocks, for memory reclamation based on the associated rank group and the selected data block. A storage system and computer-readable media are also provided.Type: ApplicationFiled: July 13, 2015Publication date: November 5, 2015Inventor: Ashot MELIK-MARTIROSIAN
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Publication number: 20150310921Abstract: A method applies a first set of consecutive pulses to flash memory cells in one or more flash memory devices to program the flash memory cells using a first pulse increment, a voltage of each consecutive pulse of the first set being incremented by the first pulse increment. On receiving an indication that the flash memory cells are partially programmed after the first set of consecutive pulses is applied, the first pulse increment is adjusted to an adjusted pulse increment based on a number of program/erase cycles associated with the flash memory cells. A second set of consecutive pulses to the flash memory cells is then applied using the adjusted pulse increment, a voltage of each consecutive pulse of the second set being incremented by the adjusted pulse increment.Type: ApplicationFiled: July 8, 2015Publication date: October 29, 2015Inventor: Ashot MELIK-MARTIROSIAN
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Patent number: 9082489Abstract: A method for programming a flash cell using a series of programming pulses, the method comprising providing a plurality of first successive programming pulses, wherein each of the first successive programming pulse is incremented by a first incremental amount and providing a plurality of second successive programming pulses, wherein each of the second successive programming pulses is incremented by a second incremental amount and wherein the second increment amount is smaller than the first incremental amount. A system and machine-readable media are also provided.Type: GrantFiled: January 14, 2013Date of Patent: July 14, 2015Assignee: STEC, Inc.Inventor: Ashot Melik-Martirosian
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Patent number: 9081663Abstract: A method for managing memory operations in a storage device having a plurality of data blocks, the method including steps for determining a number of invalid pages, in each of the plurality of data blocks, determining a number of page reads for each of the plurality of data blocks and determining a dwell time for each of the plurality of data blocks. In certain aspects, the method further comprises steps for selecting a data block, from among the plurality of data blocks, for memory reclamation based on the number of invalid pages, the number of page reads, and the dwell time of the selected data block. A flash storage system and computer-readable media are also provided.Type: GrantFiled: October 30, 2012Date of Patent: July 14, 2015Assignee: STEC, Inc.Inventor: Ashot Melik-Martirosian
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Patent number: 8957472Abstract: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.Type: GrantFiled: January 24, 2012Date of Patent: February 17, 2015Assignee: Spansion LLCInventors: Ashot Melik-Martirosian, Mark T. Ramsbey, Mark W. Randolph
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Patent number: 8819503Abstract: Disclosed is an apparatus and method for adjusting a memory parameter in a non-volatile memory circuit. On a trigger event, a parameter is determined in accordance with a circuit characteristic associated with the memory block. The parameter may be a new read level voltage to apply to a page of a memory block, or a program verify level voltage used to program a page of a memory block. On determining the parameter a command is sent to the memory circuit to apply the parameter to the page of the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit.Type: GrantFiled: March 9, 2011Date of Patent: August 26, 2014Assignee: STEC, Inc.Inventor: Ashot Melik-Martirosian
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Publication number: 20140229774Abstract: A method populates a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit. A desired condition limit is identified, and a first parameter is computed as a function of a first memory operation to be performed on the memory block. The first parameter is included in a parameter set, and the memory block is cycled until the operating condition reaches the desired condition limit. After cycling, a second parameter is determined as a function of a second memory operation to be performed on the memory block, and the second parameter is included in the parameter set. The steps of cycling, and determining and the including the second parameter may be repeated until a desired number of cycles/parameters are reached. A retention bake may also be performed on the memory circuit, and a bit error rate resulting from a read operation verified.Type: ApplicationFiled: April 14, 2014Publication date: August 14, 2014Applicant: STEC, Inc.Inventor: Ashot MELIK-MARTIROSIAN
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Patent number: 8748972Abstract: Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.Type: GrantFiled: June 18, 2013Date of Patent: June 10, 2014Assignee: Spansion LLCInventors: Ning Cheng, Fred Cheung, Ashot Melik-Martirosian, Kyunghoon Min, Michael Brennan, Hiroyuki Kinoshita
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Patent number: 8737141Abstract: Disclosed is an apparatus and method for determining a parameter for programming a non-volatile memory circuit. On receiving write or erase operation a parameter is determined as a function of a circuit characteristic associated with a memory block. An adjusted condition, for example, read or write time, or the standard deviation of voltage thresholds in a distribution of cells, is then determined as a function of the parameter, and a command provided to the memory circuit to use the parameter in the next write or erase operation performed on the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit.Type: GrantFiled: July 6, 2011Date of Patent: May 27, 2014Assignee: STEC, Inc.Inventor: Ashot Melik-Martirosian
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Patent number: 8656256Abstract: Disclosed is an apparatus and method for operating a multi-level cell (MLC) flash memory circuit. Data is read from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, and wherein the memory block is initially operating in the MLC mode. Error correction is performed on the read data to correct read errors in the read data. A determination is made if a number of bits corrected by the error correction exceeds a predetermined threshold value. If the number of bits corrected by the error correction exceeds the predetermined threshold value, the operating mode of the memory block is switched from the MLC mode to the SLC mode.Type: GrantFiled: July 6, 2011Date of Patent: February 18, 2014Assignee: STEC, Inc.Inventors: Anthony D. Weathers, Richard D. Barndt, Ashot Melik-Martirosian
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Apparatus and method for determining a read level of a flash memory after an inactive period of time
Patent number: 8644099Abstract: Disclosed is an apparatus and method for determining a dwell time in a non-volatile memory circuit after a shutdown of the memory circuit. A voltage shift is calculated by comparing a first read level voltage required to read a test block stored before the shutdown and a second read level voltage required to read a second test block stored after the shutdown. A shutdown time is determined from a look up table indexed by the voltage shift and a number of program/erase cycles. The dwell time is calculated as a function of the drive temperature, a clock, and a block time stamp. Once the dwell time is calculated, a controller calculates a new read level voltage based, in part, on the dwell time and provides one or more programming commands representative of the new read level voltage to the memory circuit to read the memory circuit.Type: GrantFiled: July 8, 2011Date of Patent: February 4, 2014Assignee: STEC, Inc.Inventors: Aldo G. Cometti, Lun Bin Huang, Ashot Melik-Martirosian