Patents by Inventor Ashot Melik-Martirosian
Ashot Melik-Martirosian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7696038Abstract: Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.Type: GrantFiled: April 26, 2006Date of Patent: April 13, 2010Assignee: Spansion LLCInventors: Ning Cheng, Kuo-Tung Chang, Hiroyuki Kinoshita, Timothy Thurgate, Wei Zheng, Ashot Melik-Martirosian, Angela Hui, Chih-Yuh Yang
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Patent number: 7678674Abstract: A method of forming implants for a memory cell includes forming an oxide-nitride-oxide (ONO) stack over a substrate and implanting first impurities in the substrate adjacent each side of the ONO stack using a first implantation energy and a first tilt angle to produce first pocket implants. The method further includes implanting second impurities in the substrate adjacent each side of the ONO stack using a second implantation energy and a second tilt angle to produce second pocket implants, where the second implantation energy is substantially larger than the first implantation energy and where the second tilt angle is substantially larger than the first tilt angle.Type: GrantFiled: August 26, 2005Date of Patent: March 16, 2010Assignee: Spansion LLCInventors: Shankar Sinha, Ashot Melik-Martirosian, Ihsan Djomehri
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Patent number: 7666739Abstract: Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.Type: GrantFiled: December 20, 2006Date of Patent: February 23, 2010Assignee: Spansion LLCInventors: Chungho Lee, Ashot Melik-Martirosian, Hiroyuki Kinoshita, Kuo-Tung Chang, Sugimo Rinji, Wei Zheng
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Patent number: 7659569Abstract: A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided.Type: GrantFiled: December 10, 2007Date of Patent: February 9, 2010Assignee: Spansion LLCInventors: Wei Zheng, Kuo-Tung Chang, Sung-Yong Chung, Ashot Melik-Martirosian
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Publication number: 20100027350Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.Type: ApplicationFiled: September 11, 2009Publication date: February 4, 2010Inventors: Ashot MELIK-MARTIROSIAN, Ed RUNNION, Mark RANDOLPH, Meng DING
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Publication number: 20100020607Abstract: A method and apparatus are provided for adaptive memory cell overerase compensation. A semiconductor memory device (100) is provided for performing the adaptively compensating erase verify operation (500, 600). The memory device (100) includes at least one word line (402). One or more memory cells (200) and one or more reference cells (406, 408) are connected to the word lines (402), where the one or more reference cells (406, 408) include an erased reference cell (408) connected to each word line (402). The method (500, 600) for adaptive memory cell overerase compensation includes determining an erase verify gate voltage (506, 608) utilizing the erased reference cell(s) (408) and verifying an erase voltage (514) of the memory cells (200) in response to the erase verify gate voltage (512, 614).Type: ApplicationFiled: October 6, 2009Publication date: January 28, 2010Inventor: Ashot Melik-Martirosian
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Patent number: 7635627Abstract: Methods are provided for fabricating a memory device comprising a dual bit memory cell. The method comprises, in accordance with one embodiment of the invention, forming a gate dielectric layer and a central gate electrode overlying the gate dielectric layer at a surface of a semiconductor substrate. First and second memory storage nodes are formed adjacent the sides of the gate dielectric layer, each of the first and second storage nodes comprising a first dielectric layer and a charge storage layer, the first dielectric layer formed independently of the step of forming the gate dielectric layer. A first control gate is formed overlying the first memory storage node and a second control gate is formed overlying the second memory storage node. A conductive layer is deposited and patterned to form a word line coupled to the central gate electrode, the first control gate, and the second control gate.Type: GrantFiled: December 20, 2006Date of Patent: December 22, 2009Assignee: Spansion LLCInventors: Ning Cheng, Hiroyuki Kinoshita, Minghao Shen, Ashot Melik-Martirosian
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Patent number: 7630253Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.Type: GrantFiled: April 5, 2006Date of Patent: December 8, 2009Assignee: Spansion LLCInventors: Ashot Melik-Martirosian, Ed Runnion, Mark Randolph, Meng Ding
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Patent number: 7626869Abstract: Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.Type: GrantFiled: May 7, 2007Date of Patent: December 1, 2009Assignee: Spansion LLCInventors: Xuguang Wang, Yi He, Zhizheng Liu, Sung-Yong Chung, Darlene G. Hamilton, Ashot Melik-Martirosian, Gulzar Kathawala, Ming Sang Kwan, Mark Randolph, Timothy Thurgate
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Patent number: 7619934Abstract: A method and apparatus are provided for adaptive memory cell overerase compensation. A semiconductor memory device (100) is provided for performing the adaptively compensating erase verify operation (500, 600). The memory device (100) includes at least one word line (402). One or more memory cells (200) and one or more reference cells (406, 408) are connected to the word lines (402), where the one or more reference cells (406, 408) include an erased reference cell (408) connected to each word line (402). The method (500, 600) for adaptive memory cell overerase compensation includes determining an erase verify gate voltage (506, 608) utilizing the erased reference cell(s) (408) and verifying an erase voltage (514) of the memory cells (200) in response to the erase verify gate voltage (512, 614).Type: GrantFiled: December 20, 2006Date of Patent: November 17, 2009Assignee: Spansion LLCInventor: Ashot Melik-Martirosian
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Patent number: 7564091Abstract: A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.Type: GrantFiled: August 27, 2008Date of Patent: July 21, 2009Assignee: Spansion LLCInventors: Chungho Lee, Ashot Melik-Martirosian, Hiroyuki Kinoshita, Kuo-Tung Chang, Amol Joshi, Meng Ding
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Patent number: 7561457Abstract: A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.Type: GrantFiled: August 18, 2006Date of Patent: July 14, 2009Assignee: Spansion LLCInventors: Mark Randolph, Zhizheng Liu, Ashot Melik-Martirosian, Yi He, Shankar Sinha
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Publication number: 20090154246Abstract: Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.Type: ApplicationFiled: December 13, 2007Publication date: June 18, 2009Applicant: SPANSION LLCInventors: Zhizheng Liu, An Chen, Wei Zheng, Kuo-Tung Chang, Sung-Yong Chung, Gulzar Ahmed Kathawala, Ashot Melik-Martirosian
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Publication number: 20090146201Abstract: A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided.Type: ApplicationFiled: December 10, 2007Publication date: June 11, 2009Applicant: Spansion LLCInventors: Wei Zheng, Kuo-Tung Chang, Sung-Yong Chung, Ashot Melik-Martirosian
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Publication number: 20080315290Abstract: A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.Type: ApplicationFiled: August 27, 2008Publication date: December 25, 2008Inventors: Chungho LEE, Ashot Melik-Martirosian, Hiroyuki Kinoshita, Kuo-Tung Chang, Amol Joshi, Meng Ding
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Patent number: 7462907Abstract: A memory array and a method of increasing erase speed therein are provided. The memory array includes a plurality of memory devices organized in rows and columns, where a plurality of bitlines are oriented substantially parallel to one another along a first direction and a plurality of wordlines are oriented substantially parallel to one another along a second direction perpendicular to the first direction. Each memory device includes a pair of energy barriers within the substrate on opposite sides of the channel width. The energy barriers prevent hot holes from diffusing out from under the gate, thereby increasing erase speed.Type: GrantFiled: November 7, 2005Date of Patent: December 9, 2008Assignee: Spansion LLCInventors: Ashot Melik-Martirosian, Timothy Thurgate
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Publication number: 20080279014Abstract: Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.Type: ApplicationFiled: May 7, 2007Publication date: November 13, 2008Applicant: SPANSION LLCInventors: Xuguang Wang, Yi He, Zhizheng Liu, Sung-Yong Chung, Darlene G. Hamilton, Ashot Melik-Martirosian, Gulzar Kathawala, Ming Sang Kwan, Mark Randolph, Timothy Thurgate
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Patent number: 7443746Abstract: A memory array tester information processing system includes executing a generation block to gather drain currents and gate voltages information for a memory array, utilizing an extraction block to obtain the drain currents and the gate voltages a portion of the memory array and an entire memory array from the generation block or stored information, and executing an analysis block to operate on the drain currents and the gate voltages from the extraction block to correlate operations on the portion of the memory array and the entire memory array. The system includes utilizing a presentation block to format the information used in the analysis block and the results of the analysis block to compute a peak threshold voltage for the memory array.Type: GrantFiled: October 18, 2005Date of Patent: October 28, 2008Assignee: Spansion LLCInventor: Ashot Melik-Martirosian
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Patent number: 7432156Abstract: A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.Type: GrantFiled: April 20, 2006Date of Patent: October 7, 2008Assignee: Spansion LLCInventors: Chungho Lee, Ashot Melik-Martirosian, Hiroyuki Kinoshita, Kuo-Tung Chang, Amol Joshi, Meng Ding
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Patent number: 7414277Abstract: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of raised bitlines, where the bitlines have a lower portion formed by a first process and an upper portion formed by a second process.Type: GrantFiled: April 22, 2005Date of Patent: August 19, 2008Assignee: Spansion, LLCInventors: Ashot Melik-Martirosian, Takashi Orimoto, Mark T. Ramsbey