Patents by Inventor Asif Khan

Asif Khan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200012432
    Abstract: An agent for managing virtual machines includes a persistent storage and a processor. The persistent storage stores backup/restoration policies. The processor identifies a virtual machine of the virtual machines that is likely to fail and, in response to identifying the virtual machine, identifies backup data associated with the identified virtual machine; instantiates a clone of the identified virtual machine using the identified backup; exposes the clone while the identified virtual machine is exposed; and hides the virtual machine after the clone is exposed.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 9, 2020
    Inventors: Upanshu Singhal, Pradeep Mittal, Kumari Priyanka, Shivakumar Kunnal Onkarappa, Chakraveer Singh, Archit Seth, Rahul Bhardwaj, Chandra Prakash, Manish Sharma, Akansha Purwar, Lalita Dabburi, Shilpa Mehta, Shelesh Chopra, Asif Khan
  • Publication number: 20200012431
    Abstract: A backup agent for generating backups includes a persistent storage and a backup manager. The persistent storage stores backup/restoration policies. The backup manager obtains production host computing resource characteristics associated with production hosts; performs a computing resource analysis of the production host computing resource characteristics to obtain resource profiles for each of the production hosts; performs an availability analysis of the obtained resource profiles to determine an application-level computing resources distribution for generating the backups; coordinates generating the backups using the application-level computing resource distribution and the backup/restoration policies to obtain the backups; and stores the obtained backups in backup storage.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 9, 2020
    Inventors: Shelesh Chopra, Tushar B. Dethe, Asif Khan, Sunil Yadav, Deepthi Urs, Mahesh Reddy Av, Swaroop Shankar Dh
  • Publication number: 20200012571
    Abstract: An agent for managing virtual machines includes a persistent storage and a processor. The persistent storage stores backup/restoration policies. The processor identify an end of a backup generation session for the virtual machines; make a first determination that the backup generation was a batch type backup session and, in response to the first determination, performs a batch level continuity analysis of backups generated via the backup generation session to identify a set of backup failures of the backup generation session; performs an unscheduled batch backup generation session based on the identified set of backup failures; and remediates the backup/restoration policies using the identified set of backup failures to ensure backup continuity of all backups associated with each of the virtual machines.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 9, 2020
    Inventors: Upanshu Singhal, Shivakumar Onkarappa, Chakraveer Singh, Archit Seth, Chandra Prakash, Pradeep Mittal, Kumari Priyanka, Rahul Bhardwaj, Akansha Purwar, Lalita Dabburi, Shilpa Mehta, Shelesh Chopra, Manish Sharma, Asif Khan
  • Publication number: 20200004424
    Abstract: A backup agent for orchestrating backups of production hosts includes a persistent storage that stores backup policies and a backup manager that obtains a backup analysis request for a virtual machine hosted by the production hosts; generate a dependency graph based on: backups associated with the virtual machines, and the backup policies associated with the backups; and displays a graphical user interface, using the dependency graph, including user interactive markers based on the backups and dependency indicators interconnecting the user interactive markers. While the graphical user interface is displayed, the backup manager obtains a potential backup policy update based on a user interaction with one of the user interactive markers. After obtaining the potential backup policy update, the backup manager updates the graphical user interface to reflect the potential backup policy update. After updating the graphical user interface, the backup manager initiates generation of the backup.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Asif Khan, Shelesh Chopra, Matthew Dickey Buchman, Bharat Bhushan, Krishnendu Bagchi
  • Publication number: 20200004640
    Abstract: A computing device for backing up virtual machine data includes a persistent storage and a backup initiator. The persistent storage stores virtual machine priority groupings and backup policies associated with the virtual machine priority groupings. The backup initiator obtains write rates of virtual machines; divides the virtual machines into priority groups based on the obtained write rates; updates the virtual machine priority groupings based on the priority groups; and performs a backup of the virtual machine data based on the backup policies using the updated virtual machine priority groupings.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Upanshu Singhal, Shivakumar Kunnal Onkarappa, Chakraveer Singh, Archit Seth, Shilpa Mehta, Rahul Bhardwaj, Akansha Purwar, Lalita Dabburi, Chandra Prakash, Kumari Priyanka, Manish Sharma, Shelesh Chopra, Asif Khan, Navneet Upadhyay, Pradeep Mittal
  • Publication number: 20190377705
    Abstract: An image processor is described. The image processor includes a storage circuit to store segments of input image data received in a raster scan format. The image processor further includes a reformatting circuit to convert the segments of input image data into a block image format. The image processor further includes a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array. The two-dimensional shift register array is to store the input image data that has been formatted into the block image format. The execution lane array is to execute instructions that operate on the image data from the two-dimensional shift register array.
    Type: Application
    Filed: August 21, 2019
    Publication date: December 12, 2019
    Inventors: Asif Khan, Jason Redgrave, Neeti Desai, David Warren
  • Publication number: 20190377642
    Abstract: A decoupled backup solution for distributed databases across a failover cluster. Specifically, a method and system disclosed herein improve upon a limitation of existing backup mechanisms involving distributed databases across a failover cluster. The limitation entails restraining backup agents, responsible for executing database backup processes across the failover cluster, from immediately initiating these aforementioned processes upon receipt of instructions. Rather, due to this limitation, these backup agents must wait until all backup agents, across the failover cluster, receive their respective instructions before being permitted to initiate the creation of backup copies of their relative distributed database. Subsequently, the limitation imposes an initiation delay on the backup processes, which the disclosed method and system omit, thereby granting any particular backup agent the capability to immediately (i.e., without delay) initiate those backup processes.
    Type: Application
    Filed: June 8, 2018
    Publication date: December 12, 2019
    Inventors: Asif Khan, Matthew Dickey Buchman, Tushar B. Dethe, Deepthi Urs, Sunil Yadav, Mahesh Reddy AV, Swaroop Shankar D H, Shelesh Chopra
  • Patent number: 10503689
    Abstract: An image processor is described. The image processor includes a storage circuit to store segments of input image data received in a raster scan format from a camera. The image processor further includes a reformatting circuit to convert the segments of input image data into a block image format. The image processor further includes a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array. The two-dimensional shift register array is to store the input image data that has been formatted into the block image format. The execution lane array is to execute instructions that operate on the image data from the two-dimensional shift register array.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 10, 2019
    Assignee: Google LLC
    Inventors: Asif Khan, Jason Redgrave, Neeti Desai, David Warren
  • Patent number: 10430203
    Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include providing an identifier in response to configuring client configurable logic within the computer system.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: October 1, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Robert Michael Johnson, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Asif Khan, Nafea Bshara, Anthony Nicholas Liguori
  • Publication number: 20190293715
    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 26, 2019
    Applicant: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Christopher Joseph Pettey, Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta
  • Patent number: 10423438
    Abstract: In a multi-tenant environment, separate virtual machines can be used for configuring and operating different subsets of programmable integrated circuits, such as a Field Programmable Gate Array (FPGA). The programmable integrated circuits can communicate directly with each other within a subset, but cannot communicate between subsets. Generally, all of the subsets of programmable ICs are within a same host server computer within the multi-tenant environment, and are sandboxed or otherwise isolated from each other so that multiple customers can share the resources of the host server computer without knowledge or interference with other customers.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 24, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Islam Mohamed Hatem Abdulfattah Mohamed Atta, Mark Bradley Davis, Robert Michael Johnson, Christopher Joseph Pettey, Asif Khan, Nafea Bshara
  • Patent number: 10418511
    Abstract: Methods are provided for forming AlInGaBN material. The method can include growing an AlInGaBN layer on a substrate; removing a portion of the AlInGaBN layer from the substrate to define a plurality of AlInGaBN islands on the substrate; and growing a highly doped-AlInGaBN layer on each of the AlInGaBN islands.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: September 17, 2019
    Assignee: University of South Carolina
    Inventor: Asif Khan
  • Publication number: 20190258597
    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 22, 2019
    Inventors: Islam Atta, Christopher Joseph Pettey, Asif Khan, Robert Michael Johnson, Mark Bradley Davis, Erez Izenberg, Nafea Bshara, Kypros Constantinides
  • Patent number: 10353843
    Abstract: A device can include one of more configurable packet processing pipelines to process a plurality of packets. Each configurable packet processing pipeline can include a plurality of packet processing components, wherein each packet processing component is configured to perform one or more packet processing operations for the device. The plurality of packet processing components are coupled to a packet processing interconnect, wherein each packet processing component is configured to route the packets through the packet processing interconnect for the one or more configurable packet processing pipelines.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: July 16, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Asif Khan, Thomas A. Volpe, Robert Michael Johnson
  • Publication number: 20190213155
    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 11, 2019
    Applicant: Amazon Technologies, Inc.
    Inventors: Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Robert Michael Johnson, Mark Bradley Davis, Christopher Joseph Pettey, Nafea Bshara, Erez Izenberg
  • Patent number: 10338135
    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 2, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Christopher Joseph Pettey, Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta
  • Publication number: 20190199692
    Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.
    Type: Application
    Filed: February 27, 2019
    Publication date: June 27, 2019
    Applicant: Amazon Technologies, Inc.
    Inventors: Islam Mohamed Hatem Abdulfattah Mohamed Atta, Christopher Joseph Pettey, Nafea Bshara, Asif Khan, Mark Bradley Davis, Prateek Tandon
  • Patent number: 10326651
    Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include associating signature information with the client configurable logic for various purposes.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: June 18, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Robert Michael Johnson, Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta
  • Patent number: 10282330
    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 7, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Robert Michael Johnson, Mark Bradley Davis, Christopher Joseph Pettey, Nafea Bshara, Erez Izenberg
  • Patent number: 10282502
    Abstract: Technologies are provided for automatically performing multiple integrated circuit implementation runs with variations of input design constraints. Input design constraints can be automatically adjusted to create multiple modified versions of the design constraints. The multiple modified design constraints can be used to perform separate integrated circuit implementation runs for a given circuit design. Results of the multiple implementation runs can be analyzed, and a circuit implementation report can be generated based on the results of the runs performed with the various modified design constraints. In some embodiments, a circuit implementation recommendation can be generated based on the implementation run results. In at least some scenarios, the multiple implementation runs can be performed using multiple synthesis and implementation processes. The multiple synthesis and implementation processes can be distributed across one or more host computing devices.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: May 7, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Nafea Bshara, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Prateek Tandon, Asif Khan, Kiran Kalkunte Seshadri