Abstract: Object layout discovery outside of backup windows is described. A system receives, from a backup/restore application, a request to discover an object layout for a data object by parsing the data object. The system determines whether the object layout is stored in layout storage. The system sends, to the backup/restore application, the object layout stored in the layout storage in response to a determination that the object layout is stored in the layout storage.

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

Abstract: An electronics adapter and method are disclosed herein. The electronics adapter can include a plurality of interface ports, with each interface port from the device coupled to a processor from a plurality of processors, and a controller communicatively coupled to the interface ports. The controller may be configured to determine a function or transaction attributes, which are serviced by instructions executed by one of the processors. The controller may be further configured to determine at least one interface port on the adapter to transmit the transaction based on the function or the attributes using an updatable mapping between the function or the attributes and the interface port, and transmit a request for the transaction using the interface port for processing of the transaction by the processor coupled to the interface port.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include associating manifests with the client configurable logic for various purposes.

Abstract: Peripheral devices may implement multiple reporting modes for signal interrupts to a host system. Different reporting modes may be determined for interrupts generated at a host system. Reporting modes may be programmatically configured for various operations at the peripheral device. Reporting modes may indicate a reporting technique for transmitting an indication of the interrupt and may indicate a priority assigned to reporting the interrupt. An interrupt controller for the peripheral device may report generated interrupts according to the reporting mode determined for the interrupts.

Abstract: A controller is configured to transmit a broadcast write request on at least one bus. The broadcast write request includes an address and a value. A first logic module determines that the broadcast write request is targeting the first logic module. The first logic module stores the value at a first addressed register specified by the register address. The second logic module determines that the broadcast write request is targeting the second logic module. The second logic module stores the value at a second addressed register specified by the register address. The first and second logic modules are connected to the at least one bus.

Abstract: A dialysis machine (e.g., a peritoneal dialysis machine) may include a housing. The machine may further include a leak detector disposed in the housing, the leak detector being an electrical circuit. In response to fluid contacting the leak detector, a leak in the dialysis machine is detectable. The machine is configured to send a signal based on a short of the electrical circuit from fluid contact with the leak detector to indicate a leak condition.

Abstract: A bus controller is configured to transmit a broadcast read request on at least one bus. The broadcast read request includes an address. A first logic module determines that the broadcast read request is targeting the first logic module. The first logic module reads a first value from a first register included in the first logic module. The first register is specified by the address included in the broadcast read request. The first value is transmitted onto the at least one bus. A second logic module determines that the broadcast read request is targeting the second logic module. The second logic module reads a second value from a second register included in the second logic module. The second register is specified by the address included in the broadcast read request. The second value is transmitted onto the at least one bus.

Abstract: Methods and systems are described for generating graphical maps showing the backup degrees of data modules located across one or more client computers in a network, and directing backup and recovery operations for those data modules. According to one embodiment, the backup system sends information requests to the client computers, and receives in response the backup degrees of the data modules contained by the client computers. The backup system then generates and displays the graphical map. The backup system then can direct backup and recovery operations by sending operation requests to the client computers and updating the graphical map when necessary. Other embodiments are also described and claimed.

Abstract: An image processor is described. The image processor includes a storage circuit to store segments of input image data received in a raster scan format from a camera. The image processor further includes a reformatting circuit to convert the segments of input image data into a block image format. The image processor further includes a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array. The two-dimensional shift register array is to store the input image data that has been formatted into the block image format. The execution lane array is to execute instructions that operate on the image data from the two-dimensional shift register array.

Abstract: The following description is directed to a logic repository service supporting adaptable host logic. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic. The method can include selecting a particular host logic shell from a group of host logic shells. The particular host logic shell can be used to encapsulate the application logic when the configurable hardware is configured. Configuration data for the configurable hardware can be generated. The configuration data can include data for implementing the application logic and at least a portion of the particular host logic shell. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The configuration data can be transmitted to the host server computer in response to the second request.

Abstract: Mechanisms for managing interference in heterogeneous networks are disclosed. A macro node triggers a handover of a user equipment (UE) being serviced by the macro node to a low power node (LPN) operating in a closed access operating mode wherein the LPN provides service to member UEs. The UE is a non-member of the LPN. The macro node determines a trigger condition, and based on the trigger condition signals the LPN to provide service to the UE. The macro node also directs the UE to execute the handover to the LPN.

Abstract: Techniques are described for logging communication traffic associated with one or more devices. For example, a system bus or other interface to a device may be monitored for traffic data elements. The traffic data elements may include, for example, transaction layer packets (TLPs) for communication across a PCI Express interface, or Ethernet packets for communication over a network. The traffic data elements can be processed by a classifier module and accordingly routed to one of a plurality of circular buffers. The circular buffers may maintain state (e.g., a head pointer and a tail pointer) that identify traffic data elements that are pending and those that are completed. Thus, the circular buffers can be inspected (such as after a crash) to determine recent activity.

Abstract: Methods are provided for forming AlInGaBN material. The method can include growing an AlInGaBN layer on a substrate; removing a portion of the AlInGaBN layer from the substrate to define a plurality of AlInGaBN islands on the substrate; and growing a highly doped-AlInGaBN layer on each of the AlInGaBN islands.

Abstract: An MOCVD system for growing a semiconductor layer on a substrate is provided. The MOCVD system includes an MOCVD growth chamber defined by a jacket having an interior surface and an exterior surface; a water flow chamber surrounding an exterior surface of the jacket of the MOCVD growth chamber; an electronic control system, wherein the electronic control system facilitates pulsed growth of the semiconductor layer; a supply tube comprising a head formed from a hollow structure defining a fitting end and an opposite, shower end, wherein the fitting end has an initial diameter that is less than a diameter at the shower end; and a susceptor configured to hold the substrate and facing the shower end of the supply tube, wherein the MOCVD system operates at a temperature greater than or equal to 1500° C.

Abstract: A conical supply tube is provided, along with deposition systems using such a tube and methods of its use. The conical supply tube includes a conical head formed from a hollow structure defining a having a fitting end and an opposite, shower end, with the fitting end has an initial diameter that is less than a diameter at the shower end. A MOCVD chamber is also generally provided that includes such a conical supply tube and a susceptor configured to hold a substrate facing the shower end of the conical supply tube. Methods are provided for growing a group III nitride layer on a surface of a substrate.

Abstract: An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlxGa1-xN, where 0<x?1 having a thickness from about 10 ?m to about 3 mm and defining apertures in the thickness of the buffer layer formed due to lateral overgrowth of the buffer layer over a grooved basal substrate. A n-junction LED layer overlying the buffer layer, a multiple quantum well LED layer overlying the n-junction LED layer, and a p-junction LED layer overlying the multiple quantum well LED layer are also included in the chip, where all of the LED layers comprise AlxGa1-xN, where 0<x?1.

Abstract: A device can include one of more configurable packet processing pipelines to process a plurality of packets. Each configurable packet processing pipeline can include a plurality of packet processing components, wherein each packet processing component is configured to perform one or more packet processing operations for the device. The plurality of packet processing components are coupled to a packet processing interconnect, wherein each packet processing component is configured to route the packets through the packet processing interconnect for the one or more configurable packet processing pipelines.