Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

Abstract: In a multi-tenant environment, separate virtual machines can be used for configuring and operating different subsets of programmable integrated circuits, such as a Field Programmable Gate Array (FPGA). The programmable integrated circuits can communicate directly with each other within a subset, but cannot communicate between subsets. Generally, all of the subsets of programmable ICs are within a same host server computer within the multi-tenant environment, and are sandboxed or otherwise isolated from each other so that multiple customers can share the resources of the host server computer without knowledge or interference with other customers.

Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Abstract: A multi-tenant environment is described with configurable hardware logic (e.g., a Field Programmable Gate Array (FPGA)) positioned on a host server computer. For communicating with the configurable hardware logic, an intermediate host integrated circuit (IC) is positioned between the configurable hardware logic and virtual machines executing on the host server computer. The host IC can include management functionality and mapping functionality to map requests between the configurable hardware logic and the virtual machines. Shared peripherals can be located either on the host IC or the configurable hardware logic. The host IC can apportion resources amongst the different configurable hardware logics to ensure that no one customer can over consume resources.

Abstract: An electronics adapter, system, and methods for using multiple interface ports to execute a single function are disclosed herein. The electronics adapter may include multiple interface ports, each having a transmission capacity for data transmitted via each interface port. Processing logic may be coupled to the two or more interface ports, to execute processes associated with the multiple interface ports utilizing a bandwidth. The electronics adapter may further include a controller to configure and merge the data from the multiple interface ports based at least in part on the transmission capacities for the multiple interface ports to support the bandwidth of the processes.

Abstract: An electronics adapter and method are disclosed herein. The electronics adapter can include a plurality of interface ports, with each interface port from the device coupled to a processor from a plurality of processors, and a controller communicatively coupled to the interface ports. The controller may be configured to determine a function or transaction attributes, which are serviced by instructions executed by one of the processors. The controller may be further configured to determine at least one interface port on the adapter to transmit the transaction based on the function or the attributes using an updatable mapping between the function or the attributes and the interface port, and transmit a request for the transaction using the interface port for processing of the transaction by the processor coupled to the interface port.

Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).

Abstract: One or more resources for an SoC can be directly mapped to a host address space in a host system as peripheral bus functions. A translation unit can provide translation between the host address space and an SoC address space for transactions targeted for a resource from the one or more resources to facilitate performing the transactions with the resource using the host address space. Some embodiments of the technology can provide peer to peer capability for communication between the SoC resources using the translation unit.

Abstract: A template for a semiconductor device is made by providing an AGN substrate, growing a first layer of Group III nitrides on the substrate, depositing a thin metal layer on the first layer, annealing the metal such as gold so that it agglomerates to form a pattern of islands on the first layer; transferring the pattern into the first layer by etching then removing excess metal; and then depositing a second Group III nitride layer on the first layer. The second layer, through lateral overgrowth, coalesces over the gaps in the island pattern leaving a smooth surface with low defect density. A Group III semiconductor device may then be grown on the template, which may then be removed. Chlorine gas may be used for etching the pattern in the first layer and the remaining gold removed with aqua regia.

Abstract: An MOCVD system for growing a semiconductor layer on a substrate is provided. The MOCVD system includes an MOCVD growth chamber defined by a jacket having an interior surface and an exterior surface; a water flow chamber surrounding an exterior surface of the jacket of the MOCVD growth chamber; an electronic control system, wherein the electronic control system facilitates pulsed growth of the semiconductor layer; a supply tube comprising a head formed from a hollow structure defining a fitting end and an opposite, shower end, wherein the fitting end has an initial diameter that is less than a diameter at the shower end; and a susceptor configured to hold the substrate and facing the shower end of the supply tube, wherein the MOCVD system operates at a temperature greater than or equal to 1500° C.

Abstract: An ID tag is disposed on a plurality of components of a machine. A controller stores a usage threshold for each component, receives signals from an ID tag reader, and associates an identification number from each ID tag with a component of the machine. The controller determines previous usage data for each component, determines an extent of usage of the machine since generation of the previous usage data, determines current usage data for each component based upon the extent of usage of the machine and the previous usage data, and compares the current usage data for each component to the usage threshold for each component. The controller generates an alert for each component in which the current usage data for that component exceeds its usage threshold and transmits the alert to a system remote from the machine.

Abstract: Server computers often include one or more input/output (I/O) adapter devices for communicating with a network or directly attached storage device. The data transfer latency for request can be reduced by utilizing ingress data placement logic to bypass the processor of the I/O adapter device. For example, host memory descriptors can be stored in a content addressable memory unit of the I/O adapter device to facilitate placement of requested data.

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.

Abstract: Techniques are described for managing virtual machines using input/output (I/O) device logging. For example, a system bus or other interface to a device may be monitored for traffic data elements. The traffic data elements may include, for example, transaction layer packets (TLPs) for communication across a PCI Express interface, or TCP/IP packets for communication over a network. These traffic data elements may be logged in an I/O device logging buffer. The I/O device logging buffer can then be used to ensure that all memory relating to a virtual machine is copied when transferring the virtual machine to another computing device. In addition, the I/O device logging buffer can be used to stop a virtual machine without waiting for the virtual machine to complete I/O processing.

Abstract: A polymorphic surface may be provided by applying at least one magnetic field across a plurality of movable surface contour elements and selectively passing a current through the magnetic field(s) adjacent selected surface contour elements, with the current being perpendicular to the magnetic field. The current interacts with the magnetic field to generate a Lorentz force driving guided substantially linear motion of the respective surface contour element(s). The surface contour elements may be individually moveable and individually selectable for application of current to generate movement. The surface contour elements may be supported in position after removing the current. The current applied across each selected surface contour element may be varied to control the amount of guided substantially linear motion.

Abstract: A polymorphic surface may be provided by applying at least one magnetic field across a plurality of movable surface contour elements and selectively passing a current through the magnetic field(s) adjacent selected surface contour elements, with the current being perpendicular to the magnetic field. The current interacts with the magnetic field to generate a Lorentz force driving guided substantially linear motion of the respective surface contour element(s). The surface contour elements may be individually moveable and individually selectable for application of current to generate movement. The surface contour elements may be supported in position after removing the current. The current applied across each selected surface contour element may be varied to control the amount of guided substantially linear motion.

Abstract: A system and method for performing event stream processing is described. A plurality of event streams are received from a plurality of input adapters, at least a first input adapter of the plurality of input adapters being located on a separate and distinct virtual machine than a second input adapter of the plurality of input adapters. Event stream data from the first input adapter and event stream data from the second input adapter are transformed into data of a single data type. The transformed data is stored in an in-memory database. Then real-time analysis is performed on the transformed data by accessing windows of the transformed data from the in-memory database based on rules defined in the event stream processing engine.