Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that require an operation voltage. The memory devices are capable of obtaining the operation voltage either from a power supply external to the memory device or from respective charge pumps internal to the memory devices. The processor is configured to predict storage activity in the memory devices, and to cause the memory devices to select a source for the operation voltage between the power supply and the respective charge pumps in accordance with the predicted storage activity.

Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.

Abstract: A memory system includes an interface and storage circuitry. The interface is configured to communicate with memory cells that store data. The storage circuitry is configured to program a data unit to a first group of the memory cells, to read the data unit from the first group using at least a read threshold to produce a first readout, and in response to detecting that reading the data unit has failed because the read threshold has fallen outside a supported range of read thresholds, due to a temperature difference between a time of programming the first group and a time of reading the first group, to program a second group of the memory cells. The circuitry is further configured to re-read the data unit from the first group using the at least read threshold to produce a second readout, and to recover the data unit from the second readout.

Abstract: A memory controller includes an interface and circuitry. The interface is configured to communicate with a memory device, which includes multiple memory cells, and which applies refreshing to the memory cells by repeatedly inverting data stored in the memory cells. The circuitry is configured to store input data in a group of the memory cells, to read the stored input data from the group of the memory cells to produce read data, the read data has an actual polarity that is either un-inverted or inverted due to the refreshing of the memory cells in the group, to analyze the read data for identifying the actual polarity of the read data, and to recover the input data from the read data based on the identified actual polarity.

Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that require an operation voltage. The memory devices are capable of obtaining the operation voltage either from a power supply external to the memory device or from respective charge pumps internal to the memory devices. The processor is configured to predict storage activity in the memory devices, and to cause the memory devices to select a source for the operation voltage between the power supply and the respective charge pumps in accordance with the predicted storage activity.

Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.

Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that require an operation voltage. The memory devices are capable of obtaining the operation voltage either from a power supply external to the memory device or from respective charge pumps internal to the memory devices. The processor is configured to predict storage activity in the memory devices, and to cause the memory devices to select a source for the operation voltage between the power supply and the respective charge pumps in accordance with the predicted storage activity.

Abstract: A method for designing a patterning process for a three-dimensional (3D) memory includes defining a target 3D structure of the 3D memory, to be applied in a periodic structure of layers on a substrate. The target 3D structure is converted into a sequence of multiple steps, each step specifying a respective pattern to be removed and a respective number of the layers to be removed from the periodic structure under the respective pattern. The sequence of steps is sent to one or more manufacturing tools.

Abstract: In a nonvolatile memory (NVM) cell, an injector having one or more layers of material with a lower potential barrier for holes is disposed between a charge storage stack and a source of holes (the gate for top injection, the substrate for bottom injection), to facilitate hole tunneling from the source of holes into the charge-storage layer of the charge storage stack. The injector has a barrier potential for holes which is less than an insulating layer of the charge-storage stack which is oriented towards the source of holes. A multi-layer crested barrier injector may have layers of increasing potential barriers for holes from the source to the charge-storage layer. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.

Abstract: Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.

Abstract: Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.

Abstract: A method for fabricating a non-volatile memory array includes placing contacts over bit lines in a self-aligned manner. The placing includes forming self-aligned contact holes bounded by a second insulating material resistant to the removal of a first insulating material previously deposited over the bit lines, and depositing contact material, wherein the second insulating material blocks effusion of the contact material beyond the contact holes. The distance between neighboring bit lines in the array does not include a margin for contact misalignment.

Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Abstract: The present invention is a method circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array. One or more NVM cells of a memory array may be erased using an erase pulse produced by a controller and/or erase pulse source adapted to induce and/or invoke a substantially stable channel current in the one or more NVM cells during an erasure procedure. The voltage profile of an erase pulse may be predefined or the voltage profile of the erase pulse may be dynamically adjusted based on feedback from a current sensor during an erase procedure.

Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Abstract: An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.

Abstract: In a nonvolatile memory (NVM) cell, an injector having one or more layers of material with a lower potential barrier for holes is disposed between a charge storage stack and a source of holes (the gate for top injection, the substrate for bottom injection), to facilitate hole tunneling from the source of holes into the charge-storage layer of the charge storage stack. The injector has a barrier potential for holes which is less than an insulating layer of the charge-storage stack which is oriented towards the source of holes. A multi-layer crested barrier injector may have layers of increasing potential barriers for holes from the source to the charge-storage layer. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.

Abstract: Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.

Abstract: Two or more erase sectors (blocks) in a given physical sector of the array. When (after) erasing a target block, determining whether a neighbor block needs to be refreshed by checking a sub-population of Vt distributions at a given program level. Various timings and strategies for performing the refresh operation are disclosed. The effects of word line disturb (gate disturb) may thereby be reduced.