Abstract: A method for creating a non-volatile memory array includes generating polysilicon columns on top of an oxide-nitride-oxide (ONO) layer, creating spacing elements on the sides of the polysilicon columns, implanting bit lines into the substrate at least between the spacing elements, depositing oxide filler over the bit lines, depositing a second polysilicon layer over the array and etching the second polysilicon layer into word lines and the polysilicon columns between the word lines.

Abstract: The present invention is a method circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array. One or more NVM cells of a memory array may be erased using an erase pulse produced by a controller and/or erase pulse source adapted to induce and/or invoke a substantially stable channel current in the one or more NVM cells during an erasure procedure.

Abstract: A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor T1 and an NMOS transistor T2, the PMOS transistors T1 sharing a common deep N well and the NMOS transistors T2 connected to a P well, wherein during negative charging, the NMOS transistors T2 shunt leakage current to ground, and during positive charging, the PMOS transistors T1 shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.

Abstract: A method for operating on bits of a memory cell, the method comprising providing a memory cell that has two separated and separately chargeable areas on first and second sides of the cell, each chargeable area defining one bit, applying an injection pulse and a verify pulse on the first side of the cell, and before the first side of the cell has reached a verify level, applying an injection pulse and a verify pulse on the second side of the cell.

Abstract: A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

Abstract: A method for operating on bits of a memory cell, the method comprising providing a memory cell that has two separated and separately chargeable areas on first and second sides of the cell, each chargeable area defining one bit, applying an injection pulse and a verify pulse on the first side of the cell, and before the first side of the cell has reached a verify level, applying an injection pulse and a verify pulse on the second side of the cell.

Abstract: An NROM memory cell is of a planar configuration without an additional oxidation being affected for the fabrication of the bit line oxide. The ONO layer is provided as a memory layer and is disposed with a uniform thickness on the semiconductor material of the source and drain regions and of the channel region, so that the ONO layer forms not only the gate dielectric, but also the insulation of the bit lines from the word lines or the gate electrode.

Abstract: A method for operating bits of memory cells in a memory array, the method including applying operating pulses to bits of a sample of memory cells, determining a response of at least one of an electrical, physical and mechanical property (e.g., threshold voltage) of the bits to the operating pulses, and applying at least one further operating pulse to the rest of the array, the at least one further operating pulse being a function of the response.

Abstract: A method for operating bits of memory cells in a memory array, the method including applying operating pulses to bits of a sample of memory cells, determining a response of at least one of an electrical, physical and mechanical property (e.g., threshold voltage) of the bits to the operating pulses, and applying at least one further operating pulse to the rest of the array, the at least one further operating pulse being a function of the response.