Abstract: An improved contact etch stop liner (CESL) is provided, to reduce stress effects in NVM cells using a nitride charge-trapping layer (such as NROM). SiON (silicon oxy-nitride) may be used in lieu of SiN (silicon nitride), for the CESL. Or, the CESL may be processed to be discontinuous, to reduce stress effects, using either conventional SiN (silicon nitride) or SiON. Or, the CESL layer may be eliminated entirely, to reduce stress effects.

Abstract: A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells threshold voltage (Vt) has been lowered to an erase verify (EV) voltage level.

Abstract: A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.

Abstract: A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.

Abstract: A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

Abstract: A buried contact etch stop layer (CESL) is disposed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The CESL may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. STI trenches may optionally be formed under the CESL. The CESL may comprise nitride or any other material that is harder (more resistant) to etch than the material on top of it.

Abstract: The present invention is a method, circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array or array segment. According to some embodiments of the present invention, one or more erase pulse parameters may be associated with each of a number of array segments within an NVM array. Separate erase pulse parameters may be associated with anywhere from one to all of the array segments within an NVM array. According to some embodiments of the present invention, a characteristic of an erase pulse (e.g. pulse amplitude, pulse duration, etc.) applied to one or more NVM cells within an array segment may be at least partially based on one or more erase pulse parameters associated with the given array segment.

Abstract: A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least partially within the contact areas and protective elements, generated when spacers are formed in the periphery area, to protect silicon under the ONO layer in the contact areas. A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area and bitline oxides whose height:distance aspect ratio (T:D) is at least 25% greater than the maximum height:distance (Tg:Dg) ratio of gate electrodes in the CMOS periphery to ensure remnants of sidewall material between bitlines after sidewall spacer etch, thus protecting silicon in a subsequent word line salicidation step.

Abstract: A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor and an NMOS transistor the PMOS transistors sharing a common deep N well and the NMOS transistors connected to a P well, wherein during negative charging, the NMOS transistors shunt leakage current to ground, and during positive charging, the PMOS transistors shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.

Abstract: An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.

Abstract: A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level of a group of history cells associated with a group of memory cells of a non-volatile memory cell array, allowing correct reading of the group of history cells, selecting a memory read reference level according to the first read reference level, and reading the non-volatile memory array cells.

Abstract: A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.

Abstract: A method for fabricating a non-volatile memory array includes placing contacts over bit lines in a self-aligned manner. The placing includes forming self-aligned contact holes bounded by a second insulating material resistant to the removal of a first insulating material previously deposited over the bit lines, and depositing contact material, wherein the second insulating material blocks effusion of the contact material beyond the contact holes. The distance between neighboring bit lines in the array does not include a margin for contact misalignment.

Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Abstract: A method for preventing fixed pattern programming, the method including programming data into a pattern of memory cells in a memory array, and preventing fixed pattern programming by periodically scrambling the data so that the data is stored in a different pattern of memory cells in the memory array.

Abstract: The present invention is a method, circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array or array segment. According to some embodiments of the present invention, one or more erase pulse parameters may be associated with each of a number of array segments within an NVM array. Separate erase pulse parameters may be associated with anywhere from one to all of the array segments within an NVM array. According to some embodiments of the present invention, a characteristic of an erase pulse (e.g. pulse amplitude, pulse duration, etc.) applied to one or more NVM cells within an array segment may be at least partially based on one or more erase pulse parameters associated with the given array segment.

Abstract: A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells threshold voltage (Vt) has been lowered to an erase verify (EV) voltage level.

Abstract: A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

Abstract: A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level of a group of history cells associated with a group of memory cells of a non-volatile memory cell array, allowing correct reading of the group of history cells, selecting a memory read reference level according to the first read reference level, and reading the non-volatile memory array cells.

Abstract: A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.