Abstract: Provided is a digital filter device that causes the last data of an immediately precedent input block to overlap with the input block of a time domain and generates an overlap block. The overlap block and the immediately precedent input block are each converted into a frequency domain block, subjected to filter processing, and converted into first and second time domain blocks. Among the overlap section of the first time domain block and the second time domain block, the front-end data of the first time domain block and the rear-end data of the temporal axis of the second time domain block are removed as a section of data that is to be removed, and output data is generated. An overlap amount is controlled on the basis of a distortion amount that is determined by comparing the removed section of the data of the first time region domain with the output section of the data of the overlap section of the second time domain block other than the removed section of said overlap section.

Abstract: Provided is a digital filter circuit in which a filter coefficient can be easily changed, for which circuit scale and power consumption can be reduced, and which carries out digital filter processing in a frequency domain.

Abstract: [Problem] A fast Fourier transform method is provided that are able to input data to be processed or output processing results in no particular order. [Solution] It is included to perform one of a process for rearranging, based on an output order setting, a plurality of output data generated by one of a fast Fourier transform and an inverse fast Fourier transform, and a process for rearranging, based on an input order setting, a plurality of input data into one of the fast Fourier transform and the inverse fast Fourier transform.

Abstract: Reduction of a circuit size and power consumption for performing digital filtering processing in a frequency domain is realized.

Abstract: Provided is an arithmetic processing apparatus and an arithmetic processing method which can perform block floating point processing with small circuit scale and high precision. A first normalization circuit (120) performs a first normalization, in which a plurality pieces of data, which have a common exponent and which are either fixed-point number representation data or mantissa portion data of block floating-point number representation, are inputted in each of a plurality of cycles and the plurality of pieces of data inputted in each of the plurality of cycles are respectively normalized with the common exponent on the basis of a maximum exponent for the plurality of pieces of data inputted in a corresponding one of the plurality of cycle. A rounding circuit (130) outputs a plurality of pieces of rounded data which are obtained by reducing a bit width of respective one of the plurality of pieces of data on which the first normalization is performed.

Abstract: [Problem] To provide a fast Fourier transform device that makes it possible to input data to be processed and output a processing result in a desired order. [Solution] A fast Fourier transform device that is provided with: a first transform means that performs a fast Fourier transform or an inverse fast Fourier transform, generates a plurality of pieces of first output data, and outputs the result in a first order; and a first data sorting processing unit that sorts the plurality of pieces of first output data that are output in the first order into a second order in accordance with an output order setting that is based on a first movement amount.

Abstract: Provided is a digital filter device that causes the last data of an immediately precedent input block to overlap with the input block of a time domain and generates an overlap block. The overlap block and the immediately precedent input block are each converted into a frequency domain block, subjected to filter processing, and converted into first and second time domain blocks. Among the overlap section of the first time domain block and the second time domain block, the front-end data of the first time domain block and the rear-end data of the temporal axis of the second time domain block are removed as a section of data that is to be removed, and output data is generated. An overlap amount is controlled on the basis of a distortion amount that is determined by comparing the removed section of the data of the first time region domain with the output section of the data of the overlap section of the second time domain block other than the removed section of said overlap section.

Abstract: A digital filter circuit includes an FFT circuit (13) that transforms a complex signal in a time domain into a signal in a frequency domain, an I/Q separation circuit (15) that separates the signal in the frequency domain into a signal in a first frequency domain that corresponds to the real part of the complex signal in the time domain, and a signal in a second frequency domain that corresponds to the imaginary part of the complex signal in the time domain, a filter circuit (21) that performs filter processing on the signal in the first frequency domain, a filter circuit (22) that performs filter processing on the signal in the second frequency domain, an I/Q combination circuit (16) that combines an output from the filter circuit (21) and an output from the filter circuit (22) to generate a signal in a third frequency domain, a filter circuit (23) that performs filter processing on the signal in the third frequency domain, and an IFFT circuit (14) that transforms an output signal from the filter circuit (23

Abstract: A digital filtering device is provided that makes it possible to reduce the size and power consumption of circuitry for filtering using FFT and IFFT. The digital filtering device includes a first filtering unit for receiving first data in a first sequence, performing a first filtering process including a fast Fourier transformation process and an inverse fast Fourier transformation process on the first data, and outputting second data in the first sequence.

Abstract: In order to reduce the power consumed when using FFT processing and filtering in the frequency domain together, a digital filter device according to the present invention is provided with: a first filtering means for performing a first fast Fourier transformation using a first data sorting process, first filtering in the frequency domain, a first inverse fast Fourier transformation using a second data sorting process, and overlap removal on a first input block including overlapped data; a second filtering means for performing a second fast Fourier transformation, which simultaneously processes all data in a second input block including overlapped data, second filtering in the frequency domain, a second inverse fast Fourier transformation, which simultaneously processes all received filtered data, and overlap removal; and a data selection means for selecting either the first filtering means or the second filtering means, wherein the operation of the filtering means that is not selected by the data selection me

Abstract: A digital filter circuit and a digital filter control method are capable of reducing circuit scale and power consumption for filter processing in a frequency domain such as an overlap FDE method.

Abstract: [Problem] A fast Fourier transform method is provided that are able to input data to be processed or output processing results in no particular order. [Solution] It is included to perform one of a process for rearranging, based on an output order setting, a plurality of output data generated by one of a fast Fourier transform and an inverse fast Fourier transform, and a process for rearranging, based on an input order setting, a plurality of input data into one of the fast Fourier transform and the inverse fast Fourier transform.

Abstract: Reduction of a circuit size and power consumption for performing digital filtering processing in a frequency domain is realized.

Abstract: A digital filter circuit includes an FFT circuit (13) that transforms a complex signal in a time domain into a signal in a frequency domain, an I/Q separation circuit (15) that separates the signal in the frequency domain into a signal in a first frequency domain that corresponds to the real part of the complex signal in the time domain, and a signal in a second frequency domain that corresponds to the imaginary part of the complex signal in the time domain, a filter circuit (21) that performs filter processing on the signal in the first frequency domain, a filter circuit (22) that performs filter processing on the signal in the second frequency domain, an I/Q combination circuit (16) that combines an output from the filter circuit (21) and an output from the filter circuit (22) to generate a signal in a third frequency domain, a filter circuit (23) that performs filter processing on the signal in the third frequency domain, and an IFFT circuit (14) that transforms an output signal from the filter circuit (23

Abstract: Provided is a semiconductor integrated circuit and an exponent calculation method that, when normalizing a plurality of data by a common exponent, speed up exponent calculation and reduce circuit scale and power consumption. When normalizing a plurality of data by a common exponent, a semiconductor integrated circuit calculates the exponent of the plurality of data. Included is a bit string generator that generates a second bit string containing bits having a transition value indicating that values of adjacent bits are different or a non-transition value indicating that values of adjacent bits are not different for each pair of adjacent bits of a first bit string constituting the data, and an exponent calculator that calculates the exponent of the plurality of data based on bit position of the transition value of a plurality of second bit strings generated from a plurality of first bit strings respectively constituting the plurality of data.

Abstract: Provided is a communication circuit (10) connected with a plurality of function blocks (A, B) that perform processing based on a first clock signal, and mediates communication between the function blocks (A, B). The communication circuit (10) includes N number of communication means, where N is a positive integer, having the same data width as communication data output from the function blocks, and each of the N number of communication means performs communication processing based on N number of second clock signals specified by 1/N of a frequency of the first clock signal, respectively corresponding to the N number of communication means and having a phase difference of 360/N degrees from each other. This makes it possible to provide a communication circuit between function blocks in which the amount of necessary hardware and power consumption is small, the timing design is easy, and the communication latency is low.

Abstract: Provided is an arithmetic processing apparatus and an arithmetic processing method which can perform block floating point processing with small circuit scale and high precision. A first normalization circuit (120) performs a first normalization, in which a plurality pieces of data, which have a common exponent and which are either fixed-point number representation data or mantissa portion data of block floating-point number representation, are inputted in each of a plurality of cycles and the plurality of pieces of data inputted in each of the plurality of cycles are respectively normalized with the common exponent on the basis of a maximum exponent for the plurality of pieces of data inputted in a corresponding one of the plurality of cycle. A rounding circuit (130) outputs a plurality of pieces of rounded data which are obtained by reducing a bit width of respective one of the plurality of pieces of data on which the first normalization is performed.

Abstract: A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.

Abstract: To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S?N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal.

Abstract: It is possible to provide a highly reliable semiconductor device and a communication method in which communication can be performed between circuits with a large degree of freedom of clock frequency which can be set in each of the circuits, a decisive operation, and a small communication latency. The semiconductor device according to the present invention includes a first circuit that performs processing based on a first clock signal, the first clock signal having a frequency M/N times as large as a frequency of a second clock signal (N is a positive integer, and M is a positive integer larger than N); a second circuit that performs processing based on the second clock signal; and a communication timing control circuit that generates a communication timing signal to control a timing at which the first circuit performs communication with the second circuit.