Patents by Inventor Atsufumi Shibayama
Atsufumi Shibayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20100052740Abstract: To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and Mare integers, includes an output clock selecting circuit (200) that selects one of three situations: an input clock signal is outputted as it is, the input clock signal is inverted and outputted and the input clock signal is not outputted; and a clock selection control circuit (100) that generates a control signal for controlling the foregoing selection of the output clock selecting circuit. The clock selection control circuit controls the foregoing selection of the output clock selecting circuit at every cycle of the input clock signal.Type: ApplicationFiled: November 9, 2007Publication date: March 4, 2010Inventors: Atsufumi Shibayama, Koichi Nose
-
Publication number: 20100042373Abstract: A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.Type: ApplicationFiled: December 19, 2007Publication date: February 18, 2010Inventors: Koichi Nose, Masayuki Mizuno, Atsufumi Shibayama
-
Patent number: 7533375Abstract: A control/data flow analysis unit analyzes the control flow and the data flow of a sequential processing program, and a fork point candidate determination unit determines fork point candidates taking this as the reference. A best fork point candidate combination determination unit determines the best fork point candidate combination by taking as the reference the result from the evaluation of the parallel execution performance of a test fork point candidate combination by a parallel execution performance evaluation unit, and a parallelized program output unit generates and outputs a parallelized program by inserting a fork command based on the best fork point candidate combination.Type: GrantFiled: March 30, 2004Date of Patent: May 12, 2009Assignee: NEC CorporationInventors: Atsufumi Shibayama, Taku Osawa, Satoshi Matsushita
-
Publication number: 20080218225Abstract: The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B.Type: ApplicationFiled: September 16, 2005Publication date: September 11, 2008Applicant: NEC CORPORATIONInventors: Atsufumi Shibayama, Koichi Nose, Masayuki Mizuno
-
Patent number: 7418583Abstract: A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.Type: GrantFiled: May 11, 2005Date of Patent: August 26, 2008Assignee: NEC CorporationInventors: Atsufumi Shibayama, Satoshi Matsushita, Sunao Torii, Naoki Nishi
-
Publication number: 20080018372Abstract: A clock converting circuit (1) receives and then converts m-phase clocks of a frequency f having a phase difference of 1/(f×m) to n-phase clocks of the frequency f having a phase difference of 1/(f×n). A single-phase clock generating circuit (2) receives the n-phase clocks of the frequency f having a phase difference equivalent time of 1/(f×n) to generate single-phase clocks in synchronism with the rising or falling edges of the n-phase clocks. Since the frequency of the m-phase clocks inputted to the clock converting circuit (1) is ‘f’, if a desired frequency of the single-phase clocks is decided, then ‘n’ can be obtained from the equation: the frequency of the single-phase clocks is equal to (f×n). This value of ‘n’ is set to the clock converting circuit (1), thereby obtaining the n-phase clocks of the frequency f from the m-phase clocks of the frequency f to provide single-phase clocks of a desired frequency.Type: ApplicationFiled: September 16, 2005Publication date: January 24, 2008Applicant: NEC CORPORATIONInventors: Koichi Nose, Masayuki Mizuno, Atsufumi Shibayama
-
Patent number: 7082601Abstract: In a parallel processor system for executing a plurality of threads in parallel to each other by a plurality of thread execution units, the respective thread execution units allow for forking of a slave thread from an individual thread execution unit into another arbitrary thread execution unit. The respective thread execution units are managed in three states, a free state where fork is possible, a busy state where a thread is being executed, and a term state where a thread being terminated and yet to be settled exists. At the time of forking of a new thread, when there exists no thread execution unit at the free state, a thread that the thread execution unit at the term state has is merged into its immediately succeeding slave thread to bring the thread execution unit in question to the free state and conduct forking of a new thread.Type: GrantFiled: July 17, 2002Date of Patent: July 25, 2006Assignee: NEC CorporationInventors: Taku Ohsawa, Atsufumi Shibayama, Satoshi Matsushita
-
Patent number: 6970997Abstract: When a processor executes a memory operation instruction by means of data dependence speculative execution, a speculative execution result history table which stores history information concerning success/failure results of the speculative execution of memory operation instructions of the past is referred to and thereby whether the speculative execution will succeed or fail is predicted. In the prediction, the target address of the memory operation instruction is converted by a hash function circuit into an entry number of the speculative execution result history table (allowing the existence of aliases), and an entry of the table designated by the entry number is referred to. If the prediction is “success”, the memory operation instruction is executed in out-of-order execution speculatively (with regard to data dependence relationship between the instructions).Type: GrantFiled: May 22, 2002Date of Patent: November 29, 2005Assignee: NEC CorporationInventors: Atsufumi Shibayama, Satoshi Matsushita, Sunao Torii, Naoki Nishi
-
Publication number: 20050216705Abstract: A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.Type: ApplicationFiled: May 11, 2005Publication date: September 29, 2005Applicant: NEC CORPORATIONInventors: Atsufumi Shibayama, Satoshi Matsushita, Sunao Torii, Naoki Nishi
-
Patent number: 6950908Abstract: The processors #0 to #3 execute a plurality of threads whose execution sequence is defined, in parallel. When the processor #1 that executes a thread updates the self-cache memory #1, if the data of the same address exists in the cache memory #2 of the processor #2 that executes a child thread, it updates the cache memory #2 simultaneously, but even if it exists in the cache memory #0 of the processor #0 that executes a parent thread, it doesn't rewrite the cache memory #0 but only records that rewriting has been performed in the cache memory #1. When the processor #0 completes a thread, a cache line with the effect that the data has been rewritten recorded from a child thread may be invalid and a cache line without such record is judged to be effective. Whether a cache line which may be invalid is really invalid or effective is examined during execution of the next thread.Type: GrantFiled: July 10, 2002Date of Patent: September 27, 2005Assignee: NEC CorporationInventors: Atsufumi Shibayama, Satoshi Matsushita
-
Patent number: 6931514Abstract: A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.Type: GrantFiled: November 28, 2001Date of Patent: August 16, 2005Assignee: NEC CorporationInventors: Atsufumi Shibayama, Satoshi Matsushita, Sunao Torii, Naoki Nishi
-
Publication number: 20040194074Abstract: A control/data flow analysis unit analyzes the control flow and the data flow of a sequential processing program, and a fork point candidate determination unit determines fork point candidates taking this as the reference. A best fork point candidate combination determination unit determines the best fork point candidate combination by taking as the reference the result from the evaluation of the parallel execution performance of a test fork point candidate combination by a parallel execution performance evaluation unit, and a parallelized program output unit generates and outputs a parallelized program by inserting a fork command based on the best fork point candidate combination.Type: ApplicationFiled: March 30, 2004Publication date: September 30, 2004Applicant: NEC CORPORATIONInventors: Atsufumi Shibayama, Taku Osawa, Satoshi Matsushita
-
Patent number: 6678789Abstract: When a load command is issued, first it is decided whether or not the subject address of the load command is stored in a storage buffer. If a hit occurs in the storage buffer, in other words if data is present which has this address, this data is output as load data. On the other hand, if no hit occurs in the storage buffer, a decision is made as to whether or not said data is stored in a cache memory, and if said data is thus stored then, along with this data being read out as load data, the load data which has been read out from this cache memory is stored in the storage buffer.Type: GrantFiled: April 4, 2001Date of Patent: January 13, 2004Assignee: NEC CorporationInventor: Atsufumi Shibayama
-
Publication number: 20030018684Abstract: In a parallel processor system for executing a plurality of threads obtained by dividing a single program in parallel to each other by a plurality of thread execution units, the respective thread execution units are connected to each other by a bus to enable forking of a slave thread from an individual thread execution unit into other arbitrary thread execution unit. The respective thread execution units are managed in three states, a free state where fork is possible, a busy state where a thread is being executed and a term state where a thread being terminated and yet to be settled exists. At the time of forking of a new thread, when there exists no thread execution unit at the free state, a thread that the thread execution unit at the term state has is merged into its immediately succeeding slave thread to bring the thread execution unit in question to the free state and conduct forking of a new thread.Type: ApplicationFiled: July 17, 2002Publication date: January 23, 2003Applicant: NEC CORPORATIONInventors: Taku Ohsawa, Atsufumi Shibayama, Satoshi Matsushita
-
Publication number: 20030014602Abstract: The processors #0 to #3 execute a plurality of threads whose execution sequence is defined, in parallel. When the processor #1 that executes a thread updates the self-cache memory #1, if the data of the same address exists in the cache memory #2 of the processor #2 that executes a child thread, it updates the cache memory #2 simultaneously, but even if it exists in the cache memory #0 of the processor #0 that executes a parent thread, it doesn't rewrite the cache memory #0 but only records that rewriting has been performed in the cache memory #1. When the processor #0 completes a thread, a cache line with the effect that the data has been rewritten recorded from a child thread may be invalid and a cache line without such record is judged to be effective. Whether a cache line which may be invalid is really invalid or effective is examined during execution of the next thread.Type: ApplicationFiled: July 10, 2002Publication date: January 16, 2003Applicant: NEC CORPORATIONInventors: Atsufumi Shibayama, Satoshi Matsushita
-
Publication number: 20020178349Abstract: When a processor executes a memory operation instruction by means of data dependence speculative execution, a speculative execution result history table which stores history information concerning success/failure results of the speculative execution of memory operation instructions of the past is referred to and thereby whether the speculative execution will succeed or fail is predicted. In the prediction, the target address of the memory operation instruction is converted by a hash function circuit into an entry number of the speculative execution result history table (allowing the existence of aliases), and an entry of the table designated by the entry number is referred to. If the prediction is “success”, the memory operation instruction is executed in out-of-order execution speculatively (with regard to data dependence relationship between the instructions).Type: ApplicationFiled: May 22, 2002Publication date: November 28, 2002Applicant: NEC CORPORATIONInventors: Atsufumi Shibayama, Satoshi Matsushita, Sunao Torii, Naoki Nishi
-
Publication number: 20020066005Abstract: The present invention provides a detector for detecting at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector is allowed to detect the at least one kind of dependence.Type: ApplicationFiled: November 28, 2001Publication date: May 30, 2002Applicant: NEC CORPORATIONInventors: Atsufumi Shibayama, Satoshi Matsushita, Sunao Torii, Naoki Nishi
-
Patent number: 6346837Abstract: In a digital delay-locked loop circuit, a variable delay circuit for delaying an input signal and generating an output signal includes a first variable delay circuit for delaying the input signal with a first delay time changed at first intervals and a second variable delay circuit for delaying the input signal with a second delay time changed at second intervals smaller than the first intervals. A phase comparator compares the phase of a feedback signal derived from the output signal with the phase of said reference signal. A counter circuit controls the first and second delay times in accordance with a difference in phase between the feedback signal and the reference signal so that the difference in phase is brought close to zero.Type: GrantFiled: September 3, 1998Date of Patent: February 12, 2002Assignee: NEC CorporationInventor: Atsufumi Shibayama
-
Patent number: 6320420Abstract: A dynamic logic element and a dynamic logic circuit realized by using such dynamic logic elements which is not affected by a clock skew and is capable of operating at high speed. The dynamic logic element comprises a detecting circuit portion which receives an output signal of the dynamic logic element fed back thereto, which detects completion of a precharge operation, and which, upon detection of completion of a precharge operation, autonomously finishes a precharge phase and starts an evaluation phase. A plurality of the dynamic logic elements are coupled in tandem to form a domino logic circuit. A plurality of the domino logic circuits are coupled in tandem without interposing a buffer circuit therebetween to realize a high speed dynamic logic circuit.Type: GrantFiled: March 23, 2000Date of Patent: November 20, 2001Assignee: NEC CorporationInventor: Atsufumi Shibayama
-
Publication number: 20010029571Abstract: When a load command is issued, first it is decided whether or not the subject address of the load command is stored in a storage buffer. If a hit occurs in the storage buffer, in other words if data is present which has this address, this data is output as load data. On the other hand, if no hit occurs in the storage buffer, a decision is made as to whether or not said data is stored in a cache memory, and if said data is thus stored then, along with this data being read out as load data, the load data which has been read out from this cache memory is stored in the storage buffer.Type: ApplicationFiled: April 4, 2001Publication date: October 11, 2001Inventor: Atsufumi Shibayama