Abstract: A global clock forming circuit for forming a global clock signal is set up on an LSI, and global clock signal is distributed on LSI by the double global clock distribution circuits cycled on the LSI in parallel with and in the inverse direction to one another. Based on the time point at the middle point of the transition point of each of the two clock signals transmitted by the global clock distribution circuit, the local clock signals are generated by the local clock generating circuits 4-(i+1), 4-(i+2), 4-j, 4-(k+1), 4-(l+1). The resulting local clock signals are distributed by the local clock distribution circuits 5-(i+1), 5-(i+2), 5-j, 5-(k+1), 5-(l+1). By this procedure, the clock signal distribution circuit can distribute low skew and high speed clock signals on a large scale integrated circuit.