Patents by Inventor Atsushi Hirose

Atsushi Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12199104
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: January 14, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Atsushi Hirose, Masashi Tsubuku, Kosei Noda
  • Publication number: 20240413166
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Application
    Filed: August 15, 2024
    Publication date: December 12, 2024
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Atsushi HIROSE, Masashi TSUBUKU, Kosei NODA
  • Publication number: 20240077773
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 7, 2024
    Inventor: Atsushi HIROSE
  • Patent number: 11754896
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: September 12, 2023
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Atsushi Hirose
  • Publication number: 20220075235
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Inventor: Atsushi HIROSE
  • Patent number: 11181793
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Publication number: 20210210519
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 8, 2021
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Atsushi HIROSE, Masashi TSUBUKU, Kosei NODA
  • Patent number: 10957714
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: March 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Atsushi Hirose, Masashi Tsubuku, Kosei Noda
  • Publication number: 20200183241
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Inventor: Atsushi HIROSE
  • Patent number: 10564499
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: February 18, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Publication number: 20190312063
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Application
    Filed: June 10, 2019
    Publication date: October 10, 2019
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Atsushi HIROSE, Masashi TSUBUKU, Kosei NODA
  • Patent number: 10424671
    Abstract: A novel semiconductor device or memory device is provided. Alternatively, a semiconductor device or memory device in which storage capacity per unit area is large is provided. The semiconductor device includes a sense amplifier provided to a semiconductor substrate and a memory cell provided over the sense amplifier. The sense amplifier includes a first transistor. The memory cell includes a capacitor over the semiconductor substrate, a second transistor provided over the capacitor, a conductor, and a groove portion. The capacitor includes a first electrode and a second electrode. The first electrode is formed along the groove portion. The second electrode has a region facing the first electrode in the groove portion. The second transistor includes an oxide semiconductor. One of a source and a drain of the second transistor is electrically connected to the second electrode through the conductor.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: September 24, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Hidekazu Miyairi, Akihisa Shimomura, Atsushi Hirose
  • Patent number: 10319744
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 11, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Atsushi Hirose, Masashi Tsubuku, Kosei Noda
  • Publication number: 20190035819
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Application
    Filed: September 18, 2018
    Publication date: January 31, 2019
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Atsushi HIROSE, Masashi TSUBUKU, Kosei NODA
  • Patent number: 10115743
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Atsushi Hirose, Masashi Tsubuku, Kosei Noda
  • Publication number: 20180149940
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Application
    Filed: January 31, 2018
    Publication date: May 31, 2018
    Inventor: Atsushi HIROSE
  • Patent number: 9885932
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventor: Atsushi Hirose
  • Patent number: 9817040
    Abstract: A minute current measurement method is provided. In the current measurement method, a first potential is applied to a first terminal of a transistor under test, a second potential is applied to a first terminal of a first transistor, the first transistor is turned on to accumulate a predetermined charge in a node electrically connecting a second terminal of the transistor under test with a second terminal of the first transistor, a third potential of an output terminal of a read circuit electrically connected to the node is measured, the first transistor is turned off, a fourth potential of the output terminal of the read circuit electrically connected to the node is measured, the amount of the charge held by the node is estimated from the amount of change in the potential of the output terminal of the read circuit (e.g.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: November 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Kazuma Furutani, Atsushi Hirose, Toshihiko Takeuchi
  • Patent number: D853919
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 16, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Saburo Hazumi, Atsushi Hirose, Ben Uk Chang
  • Patent number: D955314
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: June 21, 2022
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Atsushi Hirose, Yoshito Watanabe