Patents by Inventor Atsushi Hirose

Atsushi Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9885932
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventor: Atsushi Hirose
  • Patent number: 9817040
    Abstract: A minute current measurement method is provided. In the current measurement method, a first potential is applied to a first terminal of a transistor under test, a second potential is applied to a first terminal of a first transistor, the first transistor is turned on to accumulate a predetermined charge in a node electrically connecting a second terminal of the transistor under test with a second terminal of the first transistor, a third potential of an output terminal of a read circuit electrically connected to the node is measured, the first transistor is turned off, a fourth potential of the output terminal of the read circuit electrically connected to the node is measured, the amount of the charge held by the node is estimated from the amount of change in the potential of the output terminal of the read circuit (e.g.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: November 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Kazuma Furutani, Atsushi Hirose, Toshihiko Takeuchi
  • Publication number: 20170317112
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Application
    Filed: July 18, 2017
    Publication date: November 2, 2017
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Atsushi HIROSE, Masashi TSUBUKU, Kosei NODA
  • Patent number: 9804080
    Abstract: A color sensor with a plurality of optical sensors in which the number of terminals for connection with the outside can be reduced. The color sensor includes a plurality of optical sensors each provided with a photoelectric conversion element and an optical filter over a light-transmitting substrate. The optical filters in the plurality of optical sensors have light-transmitting characteristics different from each other. The plurality of optical sensors is mounted over an interposer including a plurality of terminal electrodes for electrical connection with an external device. The interposer includes a wiring having a plurality of branches for electrical connection between the terminal electrode for inputting a high power supply potential to the plurality of optical sensors and a wiring having a plurality of branches for electrical connection between the terminal electrode for inputting a low power supply potential to the plurality of optical sensors.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: October 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Patent number: 9742362
    Abstract: In a semiconductor device, power consumption is reduced. Further, a standby circuit is formed of a few elements, and thus increase in the circuit area of the semiconductor device is prevented. The standby circuit provided in the semiconductor device is formed of only one transistor and voltage supplied to the transistor is switched, whereby output current of the semiconductor device is controlled. As a result, the output current of the semiconductor device in a standby state can be substantially zero, so that the power consumption can be reduced. By using an oxide semiconductor for a semiconductor layer of a transistor, leakage current can be suppressed as low as possible.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 22, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Publication number: 20170235201
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Inventor: Atsushi HIROSE
  • Patent number: 9716109
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 25, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Atsushi Hirose, Masashi Tsubuku, Kosei Noda
  • Patent number: 9645463
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: May 9, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Publication number: 20170082902
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 23, 2017
    Inventor: Atsushi HIROSE
  • Patent number: 9568794
    Abstract: To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: February 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Publication number: 20170033111
    Abstract: A novel semiconductor device or memory device is provided. Alternatively, a semiconductor device or memory device in which storage capacity per unit area is large is provided. The semiconductor device includes a sense amplifier provided to a semiconductor substrate and a memory cell provided over the sense amplifier. The sense amplifier includes a first transistor. The memory cell includes a capacitor over the semiconductor substrate, a second transistor provided over the capacitor, a conductor, and a groove portion. The capacitor includes a first electrode and a second electrode. The first electrode is formed along the groove portion. The second electrode has a region facing the first electrode in the groove portion. The second transistor includes an oxide semiconductor. One of a source and a drain of the second transistor is electrically connected to the second electrode through the conductor.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 2, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Kiyoshi KATO, Hidekazu MIYAIRI, Akihisa SHIMOMURA, Atsushi HIROSE
  • Patent number: 9548133
    Abstract: A shift register circuit including a logic circuit capable of controlling the threshold voltage of a transistor and outputting a signal corresponding to an input signal by changing only the potential of a back gate without changing the potential of a gate is provided. In a shift register circuit including a logic circuit with a first transistor and a second transistor having the same conductivity type, a first gate electrode of the first transistor is connected to a source electrode or a drain electrode of the first transistor, an input signal is supplied to a second gate electrode of the first transistor, a clock signal is supplied to a gate electrode of the second transistor, and the first gate electrode and the gate electrode are formed from the same layer.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: January 17, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Patent number: 9419020
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: August 16, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Atsushi Hirose, Masashi Tsubuku, Kosei Noda
  • Publication number: 20160190176
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Application
    Filed: March 8, 2016
    Publication date: June 30, 2016
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Atsushi HIROSE, Masashi TSUBUKU, Kosei NODA
  • Publication number: 20160104734
    Abstract: To provide an imaging device in which incident light can be converted into an appropriate electric signal. The imaging device includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, and a fourth transistor. One of a source electrode and a drain electrode of the first transistor and one electrode of the photoelectric conversion element have an electrical connection portion in a first opening provided in an insulating layer positioned between the one of the source electrode and the drain electrode of the first transistor and the one electrode of the photoelectric conversion element. The number of the first opening is one in a region where the one of the source electrode and the drain electrode of the first transistor overlaps with the one electrode of the photoelectric conversion element.
    Type: Application
    Filed: October 5, 2015
    Publication date: April 14, 2016
    Inventors: Atsushi HIROSE, Yoshiyuki KUROKAWA, Takayuki IKEDA
  • Patent number: 9299724
    Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: March 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Atsushi Hirose, Masashi Tsubuku, Kosei Noda
  • Patent number: 9230952
    Abstract: A protection circuit used for a semiconductor device is made to effectively function and the semiconductor device is prevented from being damaged by a surge. A semiconductor device includes a terminal electrode, a protection circuit, an integrated circuit, and a wiring electrically connecting the terminal electrode, the protection circuit, and the integrated circuit. The protection circuit is provided between the terminal electrode and the integrated circuit. The terminal electrode, the protection circuit, and the integrated circuit are connected to one another without causing the wiring to branch. It is possible to reduce the damage to the semiconductor device caused by electrostatic discharge. It is also possible to reduce faults in the semiconductor device.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: January 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsushi Hirose, Hideaki Shishido
  • Patent number: 9209209
    Abstract: To provide a photoelectric conversion device with low power consumption and a method for operating the photoelectric conversion device. The photoelectric conversion device includes a charge storage capacitor portion, a photodiode, and a plurality of transistors. The charge storage capacitor portion is charged after being reset. Then, the charge storage capacitor portion is discharged through the photodiode or a current mirror circuit connected to the photodiode for a given period of time, and after that, the potential of the charge storage capacitor portion is read. Since power is consumed only at the time of charging, power consumption can be reduced.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: December 8, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Hirose
  • Publication number: 20150263680
    Abstract: In a semiconductor device, power consumption is reduced. Further, a standby circuit is formed of a few elements, and thus increase in the circuit area of the semiconductor device is prevented. The standby circuit provided in the semiconductor device is formed of only one transistor and voltage supplied to the transistor is switched, whereby output current of the semiconductor device is controlled. As a result, the output current of the semiconductor device in a standby state can be substantially zero, so that the power consumption can be reduced. By using an oxide semiconductor for a semiconductor layer of a transistor, leakage current can be suppressed as low as possible.
    Type: Application
    Filed: May 28, 2015
    Publication date: September 17, 2015
    Inventor: Atsushi HIROSE
  • Publication number: 20150241510
    Abstract: A minute current measurement method is provided. In the current measurement method, a first potential is applied to a first terminal of a transistor under test, a second potential is applied to a first terminal of a first transistor, the first transistor is turned on to accumulate a predetermined charge in a node electrically connecting a second terminal of the transistor under test with a second terminal of the first transistor, a third potential of an output terminal of a read circuit electrically connected to the node is measured, the first transistor is turned off, a fourth potential of the output terminal of the read circuit electrically connected to the node is measured, the amount of the charge held by the node is estimated from the amount of change in the potential of the output terminal of the read circuit (e.g.
    Type: Application
    Filed: February 19, 2015
    Publication date: August 27, 2015
    Inventors: Masashi TSUBUKU, Kazuma FURUTANI, Atsushi HIROSE, Toshihiko TAKEUCHI