Abstract: A cooling device (21) includes radiation thermometers (51 to 55), a plurality of nozzle parts, a plurality of electromagnetic valves (V1 to V5), and a control device (60). The radiation thermometers detect pre-cooling temperatures that are temperatures at a plurality of places on the mold before cooling water is sprayed from the plurality of nozzle parts to the mold. The control device individually sets a cooling time to each of the plurality of places on the mold based on a deviation between the pre-cooling temperature at the place on the mold and a target temperature and controls the electromagnetic valves based on the cooling times individually set to the plurality of respective places on the mold.

Abstract: A magnetic sensor has a Hall IC that has a Hall element formed on a surface of the Hall IC, and a lead frame that supports the Hall IC. The lead frame includes a first region that is disposed in the vicinity of the Hall element and generates a first magnetic field due to a first eddy current generated when a measurement target magnetic field is applied, and second regions that are disposed away from the first region and generate a second magnetic field having an intensity that cancels the first magnetic field by means of second eddy currents generated when the measurement target magnetic field is applied.

Abstract: A magnetic sensor has a Hall IC that has a Hall element formed on a surface of the Hall IC, and a lead frame that supports the Hall IC. The lead frame includes a first region that is disposed in the vicinity of the Hall element and generates a first magnetic field due to a first eddy current generated when a measurement target magnetic field is applied, and second regions that are disposed away from the first region and generate a second magnetic field having an intensity that cancels the first magnetic field by means of second eddy currents generated when the measurement target magnetic field is applied.

Abstract: A communication device according to an embodiment includes: a processor configured to execute a media clock for generating a frame synchronization signal having a frequency which is m times a sampling frequency; a first interface configured to output 2m-channel audio data to a DAC or receive an input of the 2m-channel audio data from an ADC, in synchronization with the frame synchronization signal; and an external counter configured to generate a frequency-divided frame synchronization signal obtained by 1/m-frequency division of the frame synchronization signal and output the frequency-divided frame synchronization signal to the DAC and the ADC.

Abstract: In order to provide a voltage abnormality detection circuit and a semiconductor device which are capable of detecting a voltage abnormality in an internal power supply voltage of the semiconductor device with a simple circuit configuration, the voltage abnormality detection circuit includes: a reference voltage circuit configured to output a first reference voltage, which is higher than the internal power supply voltage, and a second reference voltage, which is lower than the internal power supply voltage; a first voltage detection circuit configured to detect that the internal power supply voltage has exceeded a desired voltage value, with the use of the first reference voltage; and a second voltage detection circuit configured to detect that the internal power supply voltage has dropped lower than the desired voltage value, with the use of the second reference voltage.

Abstract: A current generation circuit includes: a current source circuit including a first transistor and a first resistor, and configured to output a first current based on a source voltage or a drain voltage of the first transistor and a resistance of the first resistor; a current control circuit including a voltage input terminal, a second transistor and a third transistor, and configured to output a second current based on a source voltage of the second transistor and a resistance of the third transistor; and an impedance circuit including a second resistor formed of a same resistive body as the first resistor and a fourth transistor diode-connected to the second resistor, and configured to generate a control voltage at the voltage input terminal by the first current and the second current, wherein the current generation circuit is configured to output a current based on the second current.

Abstract: A current generation circuit includes: a current source circuit including a first transistor and a first resistor, and configured to output a first current based on a source voltage or a drain voltage of the first transistor and a resistance of the first resistor; a current control circuit including a voltage input terminal, a second transistor and a third transistor, and configured to output a second current based on a source voltage of the second transistor and a resistance of the third transistor; and an impedance circuit including a second resistor formed of a same resistive body as the first resistor and a fourth transistor diode-connected to the second resistor, and configured to generate a control voltage at the voltage input terminal by the first current and the second current, wherein the current generation circuit is configured to output a current based on the second current.

Abstract: A secondary battery monitoring device is equipped with a resistance circuit and a detection circuit detecting an abnormality of a secondary battery, a current generation circuit generating a failure detection circuit for setting an output terminal of the resistance circuit to a failure diagnosis voltage, and a switch which permits the failure detection circuit to flow to the output terminal of the resistance circuit by switching. Further, a method for diagnosing failure of the secondary battery monitoring device is provided.

Abstract: A secondary battery monitoring device is equipped with a resistance circuit and a detection circuit detecting an abnormality of a secondary battery, a current generation circuit generating a failure detection circuit for setting an output terminal of the resistance circuit to a failure diagnosis voltage, and a switch which permits the failure detection circuit to flow to the output terminal of the resistance circuit by switching. Further, a method for diagnosing failure of the secondary battery monitoring device is provided.

Abstract: In order to provide a voltage abnormality detection circuit and a semiconductor device which are capable of detecting a voltage abnormality in an internal power supply voltage of the semiconductor device with a simple circuit configuration, the voltage abnormality detection circuit includes: a reference voltage circuit configured to output a first reference voltage, which is higher than the internal power supply voltage, and a second reference voltage, which is lower than the internal power supply voltage; a first voltage detection circuit configured to detect that the internal power supply voltage has exceeded a desired voltage value, with the use of the first reference voltage; and a second voltage detection circuit configured to detect that the internal power supply voltage has dropped lower than the desired voltage value, with the use of the second reference voltage.

Abstract: Provided is an overheat detection circuit configured to accurately detect a temperature of a semiconductor device even at high temperature and thus avoid outputting an erroneous detection result. The overheat detection circuit includes: a PN junction element, being a temperature sensitive element; a constant current circuit configured to supply the PN junction element with a bias current; a comparator configured to compare a voltage generated at the PN junction element and a reference voltage; a second PN junction element configured to cause a leakage current to flow through a reference voltage circuit at high temperature; and a third PN junction element configured to bypass a leakage current of the constant current circuit at the high temperature.

Abstract: Provided is a detection circuit configured to avoid erroneous detection that may occur immediately after a detection circuit is powered on. The detection circuit includes: an output transistor connected between a voltage input terminal and a voltage output terminal; and a load open-circuit detection circuit configured to detect an open circuit of a load connected to the voltage output terminal, in which an output circuit of the load open-circuit detection circuit includes a first transistor and a second transistor connected in series, the first transistor having a gate connected to the output transistor in common, the second transistor having a gate to which a signal indicating that the open-circuit of the load is detected, and in which the first transistor is in an off state when the output transistor is in an off state.

Abstract: To provide a current detection circuit capable of suppressing the occurrence of a large potential difference between input terminals of a differential amplifier circuit, and preventing degradation of input transistors. A differential amplifier circuit is equipped with a clamp circuit which limits gate-source voltages of a pair of PMOS transistors each having a bulk and a source connected to each other with the sources of the pair of PMOS transistors as input terminals.

Abstract: To provide a current detection circuit capable of suppressing the occurrence of a large potential difference between input terminals of a differential amplifier circuit, and preventing degradation of input transistors. A differential amplifier circuit is equipped with a clamp circuit which limits gate-source voltages of a pair of PMOS transistors each having a bulk and a source connected to each other with the sources of the pair of PMOS transistors as input terminals.

Abstract: Provided is a power supply voltage monitoring circuit capable of accurately detecting a power supply voltage with a small circuit scale and low power consumption. The power supply voltage monitoring circuit includes: a signal output circuit configured to output a signal voltage representing saturation characteristics with respect to an increase in power supply voltage; and a signal voltage monitoring circuit configured to output a signal representing that the signal voltage of the signal output circuit is normal, the signal voltage monitoring circuit including: a PMOS transistor including a gate connected to an output terminal of the signal output circuit; a first constant current circuit connected to a drain of the PMOS transistor; and an inverter including an input terminal connected to the drain of the PMOS transistor.

Abstract: Provided is a detection circuit configured to avoid erroneous detection that may occur immediately after a detection circuit is powered on. The detection circuit includes: an output transistor connected between a voltage input terminal and a voltage output terminal; and a load open-circuit detection circuit configured to detect an open circuit of a load connected to the voltage output terminal, in which an output circuit of the load open-circuit detection circuit includes a first transistor and a second transistor connected in series, the first transistor having a gate connected to the output transistor in common, the second transistor having a gate to which a signal indicating that the open-circuit of the load is detected, and in which the first transistor is in an off state when the output transistor is in an off state.

Abstract: Provided is a semiconductor device including a detection circuit in which, even when a load short-circuit detection circuit and a load open-circuit detection circuit perform false detection due to a fluctuation in power supply voltage and the like, an output of a false detection result can be prevented. The detection circuit includes the load short-circuit detection circuit configured to detect a short circuit of a load, the load open-circuit detection circuit configured to detect an open circuit of the load, and a logic circuit configured to output output signals of the load short-circuit detection circuit and the load open-circuit detection circuit to an output terminal of the logic circuit, in which the logic circuit outputs a signal of a non-detection logic to the output terminal when the outputs of the load open-circuit detection circuit and the load short-circuit detection circuit are detection logics.

Abstract: Provided is a power supply voltage monitoring circuit capable of accurately detecting a power supply voltage with a small circuit scale and low power consumption. The power supply voltage monitoring circuit includes: a signal output circuit configured to output a signal voltage representing saturation characteristics with respect to an increase in power supply voltage; and a signal voltage monitoring circuit configured to output a signal representing that the signal voltage of the signal output circuit is normal, the signal voltage monitoring circuit including: a PMOS transistor including a gate connected to an output terminal of the signal output circuit; a first constant current circuit connected to a drain of the PMOS transistor; and an inverter including an input terminal connected to the drain of the PMOS transistor.

Abstract: Provided is an overheat detection circuit configured to accurately detect a temperature of a semiconductor device even at high temperature and thus avoid outputting an erroneous detection result. The overheat detection circuit includes: a PN junction element, being a temperature sensitive element; a constant current circuit configured to supply the PN junction element with a bias current; a comparator configured to compare a voltage generated at the PN junction element and a reference voltage; a second PN junction element configured to cause a leakage current to flow through a reference voltage circuit at high temperature; and a third PN junction element configured to bypass a leakage current of the constant current circuit at the high temperature.

Abstract: An output circuit has a smaller area and restrains outputs from becoming unstable even if a power supply voltage is lower than an operating voltage. A supply terminal of an inverter circuit is provided with switch circuit, and the switch circuit stops the operation of the inverter circuit when the power supply voltage is lower than the operating voltage of the circuit. Further, the output terminal of the inverter circuit is provided with a current source to fix the output to the power supply voltage when the operation of the inverter circuit is stopped.