Patents by Inventor Atsushi Igarashi

Atsushi Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9059699
    Abstract: Provided is a power supply switching circuit capable of suppressing a load fluctuation such as undershoot that occurs at an output terminal at the time of power supply switching. The power supply switching circuit includes: a battery connected to the output terminal; a replica current generation circuit for generating a replica current that is proportional to a current flowing from the battery to the output terminal; a voltage regulator connected to the output terminal, the voltage regulator including a reference voltage circuit, an error amplifier circuit, an output transistor, and a voltage divider circuit; and a current mirror circuit for causing the replica current to flow through the output transistor of the voltage regulator.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: June 16, 2015
    Assignee: Seiko Instruments Inc.
    Inventors: Tsutomu Tomioka, Atsushi Igarashi, Masakazu Sugiura
  • Patent number: 9030249
    Abstract: There is provided a level shift circuit free from malfunction. The level shift circuit converts a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal. The level shift circuit has a control circuit that detects when the first power supply voltage reduces below a predetermined voltage. The voltage of the output terminal of the level shift circuit is fixed to the second power supply voltage or a ground voltage according to a detection signal of the control circuit.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: May 12, 2015
    Assignee: Seiko Instruments Inc.
    Inventors: Kosuke Takada, Atsushi Igarashi
  • Patent number: 8895140
    Abstract: Provided is a vinylidene fluoride resin film that has good adhesiveness to a base material, achieves good dispersivity even when a pigment is contained in large amounts, and has excellent thermal stability during a forming process. To a resin component composed of a vinylidene fluoride resin and a methacrylic acid ester resin, a predetermined amount of a titanium oxide surface treated with alumina and silica and a predetermined amount of a fatty acid ester of polyethylene glycol and/or its derivative are added to prepare a vinylidene fluoride resin film. Alternatively, at least a front side layer and a back side layer have such a composition, the front side layer has a combination amount of the vinylidene fluoride resin and the methacrylic acid ester resin of 70:30 to 95:5 in terms of mass ratio, and the back side layer has a combination amount of the vinylidene fluoride resin and the methacrylic acid ester resin of 5:95 to 45:55 in terms of mass ratio.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: November 25, 2014
    Assignee: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Hidetoshi Yoshimura, Fukumu Komoda, Atsushi Igarashi, Susumu Ooka, Koji Nakajima
  • Publication number: 20140232447
    Abstract: There is provided a level shift circuit free from malfunction. The level shift circuit converts a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal. The level shift circuit has a control circuit that detects when the first power supply voltage reduces below a predetermined voltage. The voltage of the output terminal of the level shift circuit is fixed to the second power supply voltage or a ground voltage according to a detection signal of the control circuit.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 21, 2014
    Applicant: Seiko Instruments Inc.
    Inventors: Kosuke TAKADA, Atsushi IGARASHI
  • Publication number: 20140084878
    Abstract: Provided is a power supply switching circuit capable of suppressing a load fluctuation such as undershoot that occurs at an output terminal at the time of power supply switching. The power supply switching circuit includes: a battery connected to the output terminal; a replica current generation circuit for generating a replica current that is proportional to a current flowing from the battery to the output terminal; a voltage regulator connected to the output terminal, the voltage regulator including a reference voltage circuit, an error amplifier circuit, an output transistor, and a voltage divider circuit; and a current mirror circuit for causing the replica current to flow through the output transistor of the voltage regulator.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 27, 2014
    Applicant: SEIKO INSTRUMENTS INC.
    Inventors: Tsutomu TOMIOKA, Atsushi IGARASHI, Masakazu SUGIURA
  • Patent number: 8604821
    Abstract: Provided is a power supply voltage monitoring circuit (50) including: a signal output circuit (1) for outputting a signal voltage (Vsignal) which exhibits a saturation characteristic with respect to an increase in a power supply voltage (VDD); and a signal voltage monitoring circuit (4) for comparing the power supply voltage (VDD) with the signal voltage (Vsignal), and outputting a signal (Vout) indicating that the signal voltage (Vsignal) is normal when there is a predetermined voltage difference. With this configuration, a minimum operating power supply voltage may be reduced in an electronic circuit, and the power supply voltage may be used with efficiency.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: December 10, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Masakazu Sugiura, Atsushi Igarashi
  • Patent number: 8547163
    Abstract: Provided is a temperature sensor device operable at a lower voltage. The temperature sensor device detects temperature based on an output voltage of a forward voltage generator for generating a forward voltage of a PN junction. The forward voltage generator includes a level shift voltage generation circuit, and an output voltage of the temperature sensor device is given based on the forward voltage of the PN junction and a voltage of the level shift voltage generation circuit.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: October 1, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Masakazu Sugiura, Atsushi Igarashi, Masahiro Mitani
  • Patent number: 8531234
    Abstract: Provided is a temperature detection device capable of attaining low current consumption at no expense of detection speed at around a temperature to be detected. The temperature detection device includes a control circuit for outputting a control signal for controlling ON/OFF of such internal circuits as a reference voltage circuit and a comparator. In the control circuit, in order to increase the detection speed at around the temperature to be detected, an oscillation frequency of an oscillation circuit has positive temperature characteristics. Further, the control circuit includes a waveform shaping circuit so as to optimize the waveform of the control signal for controlling ON of the internal circuits, to thereby attain low current consumption.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: September 10, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Masakazu Sugiura, Atsushi Igarashi
  • Patent number: 8476967
    Abstract: Provided is a constant current circuit and a reference voltage circuit with improved line regulation without needing a start-up circuit. The constant current circuit includes: a constant current generation circuit including NMOS transistors and a resistor; a current mirror circuit including a pair of depletion mode NMOS transistors, for allowing a current of the constant current generation circuit to flow; and a feedback circuit for maintaining constant voltages of source terminals of the pair of depletion mode NMOS transistors.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: July 2, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Yuji Kobayashi, Takashi Imura, Masakazu Sugiura, Atsushi Igarashi
  • Patent number: 8451571
    Abstract: Provided is a power supply integrated circuit including an overheat protection circuit with high detection accuracy. The overheat protection circuit includes: a current generation circuit including: a first metal oxide semiconductor (MOS) transistor including a gate terminal and a drain terminal that are connected to each other, the first MOS transistor operating in a weak inversion region; a second MOS transistor including a gate terminal connected to the gate terminal of the first MOS transistor, the second MOS transistor having the same conductivity type as the first MOS transistor and operating in a weak inversion region; and a first resistive element connected to a source terminal of the second MOS transistor; and a comparator for comparing a reference voltage having positive temperature characteristics and a temperature voltage having negative temperature characteristics, which are obtained based on a current generated by the current generation circuit.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: May 28, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Takashi Imura, Takao Nakashimo, Masakazu Sugiura, Atsushi Igarashi, Masahiro Mitani
  • Patent number: 8449179
    Abstract: Provided is a temperature detection system which is low in cost. The temperature detection system includes a plurality of temperature detection ICs (10) for detecting an abnormal temperature and a resistor (20). Each of the plurality of temperature detection ICs (10) includes a reference voltage terminal connected to an output terminal of one of the plurality of temperature detection ICs (10) located at a preceding stage. The resistor (20) is provided between an output terminal of one of the plurality of temperature detection ICs (10) located at the final stage and a ground terminal.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: May 28, 2013
    Assignee: Seiko Instruments Inc.
    Inventor: Atsushi Igarashi
  • Patent number: 8264277
    Abstract: Provided is a differential amplifier circuit in which an offset voltage is independent from input voltages. A first correction current generation circuit and a second correction current generation circuit are provided and configured to cause the same current as a current flowing through a folded cascode amplifying stage to flow into an output stage. Accordingly, transistors included in the folded cascode amplifying stage and transistors included in the output stage have the same bias condition.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: September 11, 2012
    Assignee: Seiko Instruments Inc.
    Inventors: Atsushi Igarashi, Masahiro Mitani
  • Publication number: 20120187911
    Abstract: An output circuit has a smaller area and restrains outputs from becoming unstable even if a power supply voltage is lower than an operating voltage. A supply terminal of an inverter circuit is provided with switch circuit, and the switch circuit stops the operation of the inverter circuit when the power supply voltage is lower than the operating voltage of the circuit. Further, the output terminal of the inverter circuit is provided with a current source to fix the output to the power supply voltage when the operation of the inverter circuit is stopped.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 26, 2012
    Inventors: Masahiro Mitani, Naohiro Hiraoka, Masakazu Sugiura, Atsushi Igarashi
  • Publication number: 20120182062
    Abstract: Provided is a temperature sensor device operable at a lower voltage. The temperature sensor device detects temperature based on an output voltage of a forward voltage generator for generating a forward voltage of a PN junction. The forward voltage generator includes a level shift voltage generation circuit, and an output voltage of the temperature sensor device is given based on the forward voltage of the PN junction and a voltage of the level shift voltage generation circuit.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 19, 2012
    Inventors: Masakazu Sugiura, Atsushi Igarashi, Masahiro Mitani
  • Publication number: 20120131402
    Abstract: Provided is a test mode setting circuit with a smaller number of terminals. A detector having a low threshold voltage and a detector having a high threshold voltage are provided to a test terminal for controlling a test mode of a semiconductor device, and the detector having the low threshold voltage releases a reset of a logic circuit while the detector having the high threshold voltage controls switching of the test mode. This configuration uses the test terminal, a reset terminal, and test mode control terminals in common between a normal state and a test state, thus reducing a large number of the terminals.
    Type: Application
    Filed: November 4, 2011
    Publication date: May 24, 2012
    Inventors: Masakazu SUGIURA, Atsushi IGARASHI
  • Publication number: 20120126873
    Abstract: Provided is a constant current circuit and a reference voltage circuit with improved line regulation without needing a start-up circuit. The constant current circuit includes: a constant current generation circuit including NMOS transistors and a resistor; a current mirror circuit including a pair of depletion mode NMOS transistors, for allowing a current of the constant current generation circuit to flow; and a feedback circuit for maintaining constant voltages of source terminals of the pair of depletion mode NMOS transistors.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 24, 2012
    Inventors: Yuji Kobayashi, Takashi Imura, Masakazu Sugiura, Atsushi Igarashi
  • Patent number: 8183907
    Abstract: Provided is a detection circuit for monitoring a power supply voltage with a circuit configuration in which power consumption is reduced, and a sensor device including the detection circuit. A detection circuit (100) detects an input signal input thereto to output an output signal. An interrupt condition generating circuit (10a) directly detects a power supply voltage (VDD) supplied thereto from a power supply, and outputs an interrupt signal until the power supply voltage makes a transition to a predetermined voltage range. An interrupt condition reception circuit outputs, as an output signal, a given voltage without allowing an input signal (Vtemp) to be output until an interrupt caused by the interrupt signal is released, and outputs, as an output signal, the input signal by allowing the input signal to be output when the interrupt caused by the interrupt signal is released.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: May 22, 2012
    Assignee: Seiko Instruments Inc.
    Inventors: Masakazu Sugiura, Atsushi Igarashi
  • Publication number: 20120105132
    Abstract: Provided is a temperature detection device capable of attaining low current consumption at no expense of detection speed at around a temperature to be detected. The temperature detection device includes a control circuit for outputting a control signal for controlling ON/OFF of such internal circuits as a reference voltage circuit and a comparator. In the control circuit, in order to increase the detection speed at around the temperature to be detected, an oscillation frequency of an oscillation circuit has positive temperature characteristics. Further, the control circuit includes a waveform shaping circuit so as to optimize the waveform of the control signal for controlling ON of the internal circuits, to thereby attain low current consumption.
    Type: Application
    Filed: September 19, 2011
    Publication date: May 3, 2012
    Inventors: Masakazu Sugiura, Atsushi Igarashi
  • Publication number: 20110293945
    Abstract: Provided is a vinylidene fluoride resin film that has good adhesiveness to a base material, achieves good dispersivity even when a pigment is contained in large amounts, and has excellent thermal stability during a forming process. To a resin component composed of a vinylidene fluoride resin and a methacrylic acid ester resin, a predetermined amount of a titanium oxide surface treated with alumina and silica and a predetermined amount of a fatty acid ester of polyethylene glycol and/or its derivative are added to prepare a vinylidene fluoride resin film. Alternatively, at least a front side layer and a back side layer have such a composition, the front side layer has a combination amount of the vinylidene fluoride resin and the methacrylic acid ester resin of 70:30 to 95:5 in terms of mass ratio, and the back side layer has a combination amount of the vinylidene fluoride resin and the methacrylic acid ester resin of 5:95 to 45:55 in terms of mass ratio.
    Type: Application
    Filed: February 9, 2010
    Publication date: December 1, 2011
    Applicant: DENKI KAGAKU KOGYO KABUSHIKI KAISHA
    Inventors: Hidetoshi Yoshimura, Fukumu Komoda, Atsushi Igarashi, Susumu Ooka, Koji Nakajima
  • Patent number: 8063675
    Abstract: Provided is a delay circuit that has a delay time period independent of a power supply voltage and has the equal delay time period between a case of a change in input signal from Low to High and a case of a change in input signal from High to Low. The delay time period is determined as a time period necessary for a voltage of a capacitor (17) (internal voltage (Va)) to increase from a ground voltage (VSS) to a voltage equal to or higher than an inverting threshold voltage of a constant current inverter (19) (threshold voltage (Vtn) of an NMOS transistor (16)). Therefore, the delay time period is determined with reference to the ground voltage (VSS). Note that the same holds true for an internal delay circuit (20). If the input signal (Vin) becomes High, the delay circuit utilizes the delay time period caused by an internal delay circuit (10). On the other hand, if the input signal (Vin) becomes Low, the delay circuit utilizes the delay time period caused by the internal delay circuit (20).
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: November 22, 2011
    Assignee: Seiko Instruments Inc.
    Inventors: Atsushi Igarashi, Masakazu Sugiura