Patents by Inventor Atsushi Ishikawa

Atsushi Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070050670
    Abstract: The present invention proposes a disk array apparatus that can be inexpensively constructed while maintaining its high reliability, and also proposes a method for controlling the disk array apparatus, and a program. In the disk array apparatus, a storage area in a storage device for storing system information is managed by dividing the storage area into a system area for storing system information and a data area for storing data from a host device, and verification processing is executed on the data area in the storage device in a first cycle and on the system area in a second cycle that is shorter than the first cycle.
    Type: Application
    Filed: October 31, 2005
    Publication date: March 1, 2007
    Inventors: Takeshi Shigemura, Seiki Morita, Atsushi Ishikawa, Yoshihiro Uchiyama
  • Publication number: 20070016901
    Abstract: When the main power source is turned on, a storage system creates a revision table for storing the revision of main firmware installed in a resource management processor of the storage system. Next, the main firmware is loaded from a system drive into a cache memory. When the revision of the main firmware installed in the resource management processor is old, this main firmware is renewed to the main firmware loaded into the cache.
    Type: Application
    Filed: September 14, 2005
    Publication date: January 18, 2007
    Inventors: Hiroshi Izuta, Seiki Morita, Atsushi Ishikawa
  • Patent number: 7142238
    Abstract: An image pick up device includes a pick-up unit for picking up an image condensed on a line sensor through a lens; a chromatic aberration correction board with a predetermined pattern in accordance with a pick-up resolution; an interpolation factor calculation unit for calculating chromatic aberration interpolation factors to be used for a chromatic aberration correction by using digital image data on the chromatic aberration correction board picked up by the pick-up unit; a line memory for storing the chromatic aberration interpolation factors calculated by the interpolation factor calculation unit; and a chromatic aberration unit for correcting the image data picked up from an original image by using the chromatic aberration interpolation factors outputted from the line memory.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: November 28, 2006
    Assignee: Minolta Co., Ltd.
    Inventors: Kenichi Sawada, Atsushi Ishikawa, Hiroyuki Suzuki
  • Publication number: 20060263541
    Abstract: The present invention provides a photoreduction method for metal complex ions by which strict controllability is not required in the control of its exposure amount, and a size of the metallic structure to be produced can be controlled, besides there is no fear of reducing spatial resolution of the size of the metallic structure to be produced. The photoreduction method for metal complex ions wherein a laser beam is beam-irradiated on a metal complex ion dispersion element dispersed in a material to photoreduce the metal complex ions thereby fabricating a metallic structure, includes the steps of adding a predetermined coloring matter to the material in which the metal complex ion dispersion element is dispersed, and beam-irradiating the laser beam to the material to which the predetermined coloring matter has been added.
    Type: Application
    Filed: May 11, 2006
    Publication date: November 23, 2006
    Applicant: RIKEN
    Inventors: Takuo Tanaka, Atsushi Ishikawa, Satoshi Kawata
  • Publication number: 20060259712
    Abstract: A storage control system comprises a first controller connected through a first access route to a first storage; a second controller connected through a second access route to a second storage device; a third controller connected through a third access route to the first storage device; and a fourth controller connected through a fourth access route to the second storage device. For example, if the access destination in accordance with the access instruction received from the host device is the second storage device, the first controller outputs an access request to the second controller. The second controller accesses the second storage device through the second access route in accordance with this access request.
    Type: Application
    Filed: September 16, 2005
    Publication date: November 16, 2006
    Inventors: Kenji Onabe, Koji Arai, Atsushi Ishikawa
  • Patent number: 7136196
    Abstract: A registered address that is normally used by the user and comprises personal information is input into an MFP apparatus. The MFP apparatus sends a command including the registered address to the mail provider, obtains a new address for which the registered address is designated as a forwarding address, and deletes the registered address from the MFP apparatus. Where the MFP apparatus receives an e-mail non-arrival notification, the MFP apparatus sends the non-arrival notification to the new address. The non-arrival notification sent to the new address is received by the mail provider and forwarded to the registered address. In this way, notification of the e-mail's non-arrival can be provided without the registered address remaining in the MFP apparatus.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: November 14, 2006
    Assignee: Minolta Co., Ltd.
    Inventor: Atsushi Ishikawa
  • Publication number: 20060214796
    Abstract: By storing check-out procedure data into a radio tag and by providing a leaving allowance judgment portion at an exit gate, it is possible to judge whether a user is allowed to leave at an exit section alone. It is thus possible to shorten a time needed for a leaving allowance judgment.
    Type: Application
    Filed: February 14, 2006
    Publication date: September 28, 2006
    Applicant: Toshiba Tec Kabushiki Kaisha
    Inventor: Atsushi Ishikawa
  • Publication number: 20060214800
    Abstract: Under the step management of a stepping motor, a move distance of an antenna of a wireless tag scanning device is calculated, and wireless tags are scanned in synchronization with a step move amount. The antenna controls its directivity using shield members etc., and lowers electromagnetic susceptibility in the moving direction. Accordingly, it becomes possible to detect a wireless tag located on a certain position, enabling position management with high resolution.
    Type: Application
    Filed: March 1, 2006
    Publication date: September 28, 2006
    Applicant: Toshiba Tec Kabushiki Kaisha
    Inventor: Atsushi Ishikawa
  • Publication number: 20060213992
    Abstract: The present invention provides a wireless tag communication control device, which includes a gate through which an object having attached thereto a wireless tag passes, a sensor that is arranged at the gate and senses the existence position of the object, an antenna that is arranged at the gate and transmits an electric wave to the wireless tag, and an electric wave output adjustment unit that is connected to the antenna, wherein an electric wave transmission output from the antenna is adjusted according to the position of the object in the gate.
    Type: Application
    Filed: March 6, 2006
    Publication date: September 28, 2006
    Applicant: TOSHIBA TEC KABUSHIKI KAISHA
    Inventor: Atsushi Ishikawa
  • Patent number: 7111134
    Abstract: A subsystem and a subsystem processing method are disclosed in which a storage control unit 2000 interposed between a plurality of disk units 3000 and a host computer 1000 has a nonvolatile cache 2400 for temporarily holding the read data/write data exchanged between the disk units 3000 and the host computer 1000. The management information for the user data in the cache 2400 is stored in both the in-cache management information area 2420 in the cache 2400 and the in-memory management information area 2221 in a volatile local memory 2210 accessible at high speed. Under normal conditions, the management information in the high speed in-memory management information area 2221 is accessed. At the time of a fault, on the other hand, the management information in the nonvolatile in-cache management information area 2420 is restored in the in-memory management information area 2221, thereby improving the access rate of the cache 2400.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: September 19, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Rie Tanaka, Atsushi Ishikawa
  • Patent number: 7064865
    Abstract: An image processing method and device includes the steps of detecting a crossing point that has a largest density value among pixels aligned in one direction and a smallest density value among pixels aligned in another direction, the directions being perpendicular to each other; determining a dot area of an image based on a detection of crossing points; and switching image data processing methods based on a result of a determination of a dot area.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: June 20, 2006
    Assignee: Minolta Co., Ltd.
    Inventor: Atsushi Ishikawa
  • Publication number: 20060112543
    Abstract: A jig for holding and conveyance having a weak-adherence adhesive pattern on a plate surface on which a printed circuit board having a conductive portion and a non-conductive portion on the surface of an insulating substrate is placed and held. The weak-adherence adhesive pattern is formed by being restricted to a position corresponding to non-conductive portion. A jig for holding and conveyance is also disclosed which has a fluorine-based resin layer on a plate surface on which a printed circuit board having a conductive pattern on the surface of an insulating substrate is placed and held. On the fluorine-based resin layer, the printed circuit board is held so that the conductor pattern surface of the printed circuit board is approximately parallel to the plate surface.
    Type: Application
    Filed: July 15, 2003
    Publication date: June 1, 2006
    Inventors: Atsushi Ishikawa, Osamu Deguchi, Katsuyoshi Kameyama, Makoto Nagaoka, Akihiro Kimura
  • Publication number: 20060113609
    Abstract: A semiconductor device, comprising: a first transistor of a second electric conductivity type formed in a substrate including impurities of a first electric conductivity type; and a second transistor of the second electric conductivity type formed in the substrate, a source region of the second transistor being shared with a source region of the first transistor; wherein in a lower layer of a gate insulating film of the first transistor, a first offset layer of the second electric conductivity type is formed adjacent to a channel region of the first transistor, in a lower layer of a gate insulating film of the second transistor, a second offset layer of the second electric conductivity type is formed adjacent to a channel region of the second transistor, and in the source region, a first diffusion layer of the first electric conductivity type and a second diffusion layer of the first electric conductivity type in the upper layer of the first diffusion layer are formed, and wherein the second diffusion layer i
    Type: Application
    Filed: October 13, 2005
    Publication date: June 1, 2006
    Inventor: Atsushi Ishikawa
  • Patent number: 7047121
    Abstract: An antiskid control system for a four-wheel-drive vehicle is arranged to calculate a difference between an average of wheel accelerations of front wheels and an average of wheel acceleration of rear wheels. When the difference is greater than or equal to the vibration determination threshold, the antiskid control system determines that a driveline vibration is generated and executes a control for converging the driveline vibration.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: May 16, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Gen Inoue, Atsushi Ishikawa, Nobuyuki Ohtsu
  • Patent number: 7017003
    Abstract: A journal write unit writes journal data into a third storage device. The journal data includes an identifier of a logical volume in a first storage device into which data has been written, information of a location in which the data is stored in the logical volume, update time which is current time acquired from a timing mechanism, and the data. A second write unit refers to update time of the journal data stored in the third storage device, selects journal data for which a difference between current time acquired from the timing mechanism and the update time is longer than a detection time stored in the third storage device, and writes the data into a place indicated by the location information, in a logical volume in the second storage device in the order of update time in the selected journal data.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: March 21, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Akira Murotani, Atsushi Ishikawa, Tetsuya Kishimoto
  • Publication number: 20060031648
    Abstract: A storage device can flexibly apply a dynamic load distribution and a performance expansion to an unexpected peak performance demand changing in a time sequence such as a web server and a contents delivery at the minimum cost. In the storage device, a load condition of a logical volume is measured by a performance measuring mechanism based on a data and command processing amounts transferred by a data transfer mechanism, and contents of the logical volume set in the physical volume are copied to a logical volume set in the auxiliary logical volume by a copy mechanism based on a measurement result of the performance measuring mechanism, and the logical volume set in the auxiliary physical volume copied by the copy mechanism and the logical volume set in the physical volume serving as a copy source are provided as one virtual logical volume in a host, thereby distributing a load from the host.
    Type: Application
    Filed: October 26, 2004
    Publication date: February 9, 2006
    Inventors: Atsushi Ishikawa, Koji Arai
  • Publication number: 20050264104
    Abstract: An antiskid control system for a four-wheel-drive vehicle is arranged to calculate a difference between an average of wheel accelerations of front wheels and an average of wheel acceleration of rear wheels. When the difference is greater than or equal to the vibration determination threshold, the antiskid control system determines that a driveline vibration is generated and executes a control for converging the driveline vibration.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 1, 2005
    Inventors: Gen Inoue, Atsushi Ishikawa, Nobuyuki Ohtsu
  • Patent number: 6956674
    Abstract: An image processor employing error diffision is provided with a multivalued dithering part, for reducing the bit number of computing in a feedback loop for errors. Thus, an operation can be performed at a high speed while the capacity of an error storage memory can be reduced.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: October 18, 2005
    Assignee: Minolta Co., Ltd.
    Inventor: Atsushi Ishikawa
  • Patent number: 6954769
    Abstract: A storage sub-system employs a staging control information table by which staging of data to be read and redundant data thereof can be executed together to reduce response time in the event of a data read failure. The staging control information table also permits pre-read staging to be executed in the forward, backward or both the forward and backward directions, to reduce response time.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: October 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Ishikawa, Yoshiko Matsumoto, Kenichi Takamoto
  • Publication number: 20050184932
    Abstract: A shift register includes M (M is an integer larger than two) stages of transfer elements and a control circuit. The M stages of the transfer elements transfer N (M>N, N is an integer larger than one) data signals sequentially input within one cycle. To the control circuit, N clock signals and a control signal are input within the one cycle and the control circuit supplies a shift clock signal to N stages of the transfer elements among the M stages of the transfer elements and supplies a skip fixed logic signal to (M-N) stages of the transfer elements among the M stages of the transfer elements based on the control signal.
    Type: Application
    Filed: January 18, 2005
    Publication date: August 25, 2005
    Inventor: Atsushi Ishikawa