Patents by Inventor Atsushi Ishikawa

Atsushi Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080128804
    Abstract: A semiconductor device, comprising: a first transistor of a second electric conductivity type formed in a substrate including impurities of a first electric conductivity type; and a second transistor of the second electric conductivity type formed in the substrate, a source region of the second transistor being shared with a source region of the first transistor; wherein in a lower layer of a gate insulating film of the first transistor, a first offset layer of the second electric conductivity type is formed adjacent to a channel region of the first transistor, in a lower layer of a gate insulating film of the second transistor, a second offset layer of the second electric conductivity type is formed adjacent to a channel region of the second transistor, and in the source region, a first diffusion layer of the first electric conductivity type and a second diffusion layer of the first electric conductivity type in the upper layer of the first diffusion layer are formed, and wherein the second diffusion layer i
    Type: Application
    Filed: January 16, 2008
    Publication date: June 5, 2008
    Inventor: Atsushi Ishikawa
  • Publication number: 20080126581
    Abstract: Provided is a storage subsystem capable of improving the data processing speed by balancing the load on processors and controllers. This storage subsystem includes a controller for controlling the input and output of data to and from a storage apparatus that provides to a host computer a plurality of logical units to become a storage extent for the host computer to read and write data, processes a command issued by the host computer, and has a storage resource in relation to the logical unit. The controller has a local memory for storing the command, and a processor configured from a plurality of cores for controlling the input and output of data to and from the logical unit to be subject to the input and output of the data based on the command. The local memory stores association information representing the correspondence between the plurality of logical units and the plurality of cores.
    Type: Application
    Filed: January 25, 2007
    Publication date: May 29, 2008
    Inventors: Kousuke Komikado, Koji Iwamitsu, Tetsuya Shirogane, Atsushi Ishikawa, Takahide Okuno, Mitsuhide Sato, Toshiaki Minami, Hiroaki Yuasa
  • Publication number: 20080126668
    Abstract: Proposed is a storage controller and its control method for speeding up the processing time in response to a command in a simple manner while reducing the load of a controller that received a command targeting a non-associated logical volume. This storage controller includes a plurality of controllers for controlling the input and output of data to and from a corresponding logical unit based on a command retained in a local memory, and the local memory stores association information representing the correspondence of the logical units and the controllers and address information of the local memory in each of the controllers of a self-system and another-system.
    Type: Application
    Filed: January 26, 2007
    Publication date: May 29, 2008
    Inventors: Takahide Okuno, Mitsuhide Sato, Toshiaki Minami, Hiroaki Yuasa, Kousuke Komikado, Koji Iwamitsu, Tetsuya Shirogane, Atsushi Ishikawa
  • Patent number: 7372444
    Abstract: The invention provides a semiconductor integrated circuit having a zooming function independently in a driver IC for driving a display device. The semiconductor integrated circuit can be a semiconductor integrated circuit which respectively outputs a plurality of two-dimensional images of different sizes according to a mode signal from a plurality of output terminals. It can include select signal shift circuits and the like which, in a first mode, synchronize with one of a rise-up or a fall of a clock signal and sequentially supply a select signal to each of select signal supply terminals, and, in a second mode, synchronize with the rise-up and the fall of the clock signal and sequentially supply the select signals to two of select signal supply terminals at a time.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: May 13, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Atsushi Ishikawa
  • Publication number: 20080091972
    Abstract: Proposed is a storage apparatus capable of alleviating the burden of maintenance work when a failure occurs in a part configuring the storage apparatus. This storage apparatus includes multiple disk drives and spare disk drives, and multiple controllers. When a failure occurs, this storage apparatus determines the operability status of the storage apparatus based on failure information. When operation can be continued, the storage apparatus continues to operate without performing any maintenance such as part replacement, and if operation cannot be continued, data is migrated to another storage apparatus.
    Type: Application
    Filed: February 6, 2007
    Publication date: April 17, 2008
    Inventors: Koichi Tanaka, Keiichi Tezuka, Atsushi Ishikawa, Azuma Kano, Koji Arai, Yusuke Nonaka
  • Patent number: 7360038
    Abstract: A storage control system comprises a first controller connected through a first access route to a first storage; a second controller connected through a second access route to a second storage device; a third controller connected through a third access route to the first storage device; and a fourth controller connected through a fourth access route to the second storage device. For example, if the access destination in accordance with the access instruction received from the host device is the second storage device, the first controller outputs an access request to the second controller. The second controller accesses the second storage device through the second access route in accordance with this access request.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: April 15, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Onabe, Koji Arai, Atsushi Ishikawa
  • Patent number: 7345348
    Abstract: A semiconductor device, comprising: a first transistor of a second electric conductivity type formed in a substrate including impurities of a first electric conductivity type; and a second transistor of the second electric conductivity type formed in the substrate, a source region of the second transistor being shared with a source region of the first transistor; wherein in a lower layer of a gate insulating film of the first transistor, a first offset layer of the second electric conductivity type is formed adjacent to a channel region of the first transistor, in a lower layer of a gate insulating film of the second transistor, a second offset layer of the second electric conductivity type is formed adjacent to a channel region of the second transistor, and in the source region, a first diffusion layer of the first electric conductivity type and a second diffusion layer of the first electric conductivity type in the upper layer of the first diffusion layer are formed, and wherein the second diffusion layer i
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: March 18, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Atsushi Ishikawa
  • Publication number: 20080061497
    Abstract: An object of the present invention is to provide a cash handling machine which opens and closes a shutter in correspondence to a condition of a money amount approval by a user, keeps a security and can strictly manage the cash. A bank bill storing machine is constituted by an upper unit executing a counting process and a lower unit keeping bank bills, the upper unit is provided with an openable temporary reservation tray arranged in a temporary reservation portion temporarily accumulating bank bills to be received, the lower unit is covered by a safe-shaped covering member and is provided with a shutter for security which can be opened and closed, and a bank bill storage shutter which can be opened and closed automatically or manually is arranged in a bank bill storage receiving the bank bills to be received.
    Type: Application
    Filed: May 1, 2006
    Publication date: March 13, 2008
    Inventors: Atsushi Ishikawa, Kuniyuki Tanaka, Shinichi Matsuyama
  • Patent number: 7337200
    Abstract: A storage sub-system employs a staging control information table by which staging of data to be read and redundant data thereof can be executed together to reduce response time in the event of a data read failure. The staging control information table also permits pre-read staging to be executed in the forward, backward or both the forward and backward directions, to reduce response time.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: February 26, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Ishikawa, Yoshiko Matsumoto, Kenichi Takamoto
  • Patent number: 7328326
    Abstract: A storage device can flexibly apply a dynamic load distribution and a performance expansion to an unexpected peak performance demand changing in a time sequence such as a web server and a contents delivery at the minimum cost. In the storage device, a load condition of a logical volume is measured by a performance measuring mechanism based on a data and command processing amounts transferred by a data transfer mechanism, and contents of the logical volume set in the physical volume are copied to a logical volume set in the auxiliary logical volume by a copy mechanism based on a measurement result of the performance measuring mechanism, and the logical volume set in the auxiliary physical volume copied by the copy mechanism and the logical volume set in the physical volume serving as a copy source are provided as one virtual logical volume in a host, thereby distributing a load from the host.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: February 5, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Ishikawa, Koji Arai
  • Patent number: 7322969
    Abstract: A liquid-medicine injection port device includes: a liquid-medicine inlet which is formed at its upper end; a liquid-medicine outlet which is formed at its lower end which is connectable to a liquid-medicine container; a liquid passageway which connects the liquid-medicine inlet and the liquid-medicine outlet; a germ-removal filter which is provided in the liquid passageway; and a closure which closes the liquid passageway downstream from the germ-removal filter and opens it easily. Further, a liquid-medicine container is provided with this liquid-medicine injection port device. Or further, the liquid-medicine container has a two-chamber structure in which an injection chamber provided with the liquid-medicine injection port device which the germ-removal filter is attached to, and a storage chamber storing a liquid medicine are divided by a weak seal portion having such a strength that it is easily peeled.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: January 29, 2008
    Assignee: Nipro Corporation
    Inventors: Hiroyuki Hattori, Takamitsu Ohkawara, Atsushi Ishikawa
  • Publication number: 20070288712
    Abstract: Proposed is a storage apparatus and its control method capable of performing dynamic load balancing or performance acceleration as a whole by balancing the load to a logical volume. With this storage apparatus, the load status of the volume is measured based on the data volume and command throughput transferred between the higher-level device and the storage unit. In addition, the contents of the volume having a load exceeding the default value are copied to one or more backup volumes based on the measurement results of the load status of the volume, the volume of a copy source and the backup volume of a copy destination are associated with one virtual volume, and the virtual volume is provided to the higher-level device.
    Type: Application
    Filed: August 3, 2006
    Publication date: December 13, 2007
    Inventors: Yoshifumi Zimoto, Ikuya Yagisawa, Atsushi Ishikawa
  • Publication number: 20070266556
    Abstract: A part cartridge for a mounter device used in a mounting process for mounting electronic parts on a substrate by heating the substrate to a predetermined temperature after the electronic parts are mounted on the substrate put on a conveying carrier by the mounter device, comprising holding part holding the substrate in the state of being fitted to the conveying carrier, and a guide tape holding the holding part. The holding member is stored in the state of being wound together with the guide tape so that the holding part can be mounted on the conveying carrier by the mounter device. By this, a method of holding and carrying the substrate for mounting the holding part on the conveying carrier by using the mounter device can be adopted in the mounting process. The deflection of the substrate in reflow can be securely prevented while suppressing cost by effectively utilizing the existing mounting line and devices.
    Type: Application
    Filed: July 9, 2004
    Publication date: November 22, 2007
    Applicant: DAISHO DENSHI CO., LTD.
    Inventors: Akihiro Kimura, Osamu Deguchi, Koji Annou, Atsushi Ishikawa
  • Publication number: 20070182560
    Abstract: If the frequency of the electric waves used at a pre-designated inspection site is known frequency, the antenna seal connected to a base antenna is peeled off, in part or entirety. Thus, the resonance frequency is easily and correctly adjusted to the frequency known.
    Type: Application
    Filed: January 31, 2007
    Publication date: August 9, 2007
    Applicant: TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Hidekazu Mori, Atsushi Ishikawa, Satoshi Ohishi
  • Patent number: 7254283
    Abstract: In order to efficiently process image data in a circuit dividing single image data into a plurality of data and processing the data with a plurality of MPUs in parallel with each other, the MPUs process image data input through an input image data in parallel with each other. An address bus inputs addresses of the image data, and address memories provided on the MPUs store the addresses of the image data processed by the MPUs respectively. When the image data are completely processed, the image data are output through an output image bus while the addresses of the image data are output through the address bus.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: August 7, 2007
    Assignee: Minolta Co., Ltd.
    Inventors: Junji Nishigaki, Atsushi Ishikawa, Kenichi Sawada, Kazuhiro Ishiguro, Hiroyuki Suzuki
  • Publication number: 20070082626
    Abstract: An integrated circuit device includes an I/O circuit which buffers and outputs an input signal D from a pad when an enable signal ENB is set at a second voltage level, a circuit block to which an output signal from the I/O circuit is input, and a malfunction prevention circuit which outputs to the circuit block an output signal QP of which a voltage level is set by a first power supply VDDC in a period T1 in which the signal ENB is set at a first voltage level and a period T2 including a period in which the signal ENB changes from the first voltage level to the second voltage level, and outputs to the circuit block the output signal QP corresponding to an output signal QI from the I/O circuit in a period T3 in which the signal ENB is set at the second voltage level.
    Type: Application
    Filed: October 10, 2006
    Publication date: April 12, 2007
    Inventors: Hiroaki Nomizo, Atsushi Ishikawa, Tsuyoshi Tamura
  • Publication number: 20070067666
    Abstract: A disk array system, upon detecting a failure in any data disk from among a plurality of data disks providing one or more RAID groups, conducting a correction copy to any spare disk, using one or more other data disks belonging to the same RAID group as the data disk causing the failure. When the data disk causing the failure has been replaced with a new data disk, the disk array system alters the management so that the data disk can be managed as a spare disk, and the spare disk can be managed as a data disk.
    Type: Application
    Filed: November 16, 2005
    Publication date: March 22, 2007
    Inventors: Atsushi Ishikawa, Kenji Onabe
  • Publication number: 20070050670
    Abstract: The present invention proposes a disk array apparatus that can be inexpensively constructed while maintaining its high reliability, and also proposes a method for controlling the disk array apparatus, and a program. In the disk array apparatus, a storage area in a storage device for storing system information is managed by dividing the storage area into a system area for storing system information and a data area for storing data from a host device, and verification processing is executed on the data area in the storage device in a first cycle and on the system area in a second cycle that is shorter than the first cycle.
    Type: Application
    Filed: October 31, 2005
    Publication date: March 1, 2007
    Inventors: Takeshi Shigemura, Seiki Morita, Atsushi Ishikawa, Yoshihiro Uchiyama
  • Publication number: 20070016901
    Abstract: When the main power source is turned on, a storage system creates a revision table for storing the revision of main firmware installed in a resource management processor of the storage system. Next, the main firmware is loaded from a system drive into a cache memory. When the revision of the main firmware installed in the resource management processor is old, this main firmware is renewed to the main firmware loaded into the cache.
    Type: Application
    Filed: September 14, 2005
    Publication date: January 18, 2007
    Inventors: Hiroshi Izuta, Seiki Morita, Atsushi Ishikawa
  • Patent number: 7142238
    Abstract: An image pick up device includes a pick-up unit for picking up an image condensed on a line sensor through a lens; a chromatic aberration correction board with a predetermined pattern in accordance with a pick-up resolution; an interpolation factor calculation unit for calculating chromatic aberration interpolation factors to be used for a chromatic aberration correction by using digital image data on the chromatic aberration correction board picked up by the pick-up unit; a line memory for storing the chromatic aberration interpolation factors calculated by the interpolation factor calculation unit; and a chromatic aberration unit for correcting the image data picked up from an original image by using the chromatic aberration interpolation factors outputted from the line memory.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: November 28, 2006
    Assignee: Minolta Co., Ltd.
    Inventors: Kenichi Sawada, Atsushi Ishikawa, Hiroyuki Suzuki