Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

Abstract: According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory stores data pieces and search information including entries, where each entry is associated with a search key for specifying one data piece and a real address at which the data piece is stored. Upon reception of a first command, the controller, when the first command specifies a search key, outputs one data piece corresponding to one entry which includes the search key, and when the first command specifies one real address, outputs one data piece corresponding to one entry including the real address.

Abstract: According to one embodiment, a memory device is connectable to a host device. The memory device includes a first interface unit, a controller unit, a second memory and a second interface. The first interface unit receives a write command from the host device. The controller unit acquires the write-data associated with the write command stored in a first memory area of a first memory in the host device, the write-data being copied from a second memory area of the first memory. The second interface causes the second memory to write the write-data in the second memory.

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

Abstract: An entertainment device includes a general-purpose signal processor made up of an assembly of component-processors, each of which can operate in parallel under operating environments independent of others component-processors. A management processor controls a cross bar so as to change the operating environments of the respective component-processors in accordance with a demand for signal processing which is given from a CPU, and to change over any one of the component-processors which receives a signal to be processed which is inputted through the cross bar or outputs a processed signal in accordance with the demand for signal processing.

Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

Abstract: According to one embodiment, a memory system includes nonvolatile memories each storing data and an address table for acquiring an address of the data, and a control unit which is configured to be capable of accessing the nonvolatile memories in parallel, and issues table read requests for reading the address tables and data read requests for reading the data to the nonvolatile memories in response to read commands from a host. When a table read request and a data read request are issued to a same nonvolatile memory, the control unit processes the data read request in priority to the table read request.

Abstract: A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

Abstract: According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data.

Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

Abstract: According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data.

Abstract: According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data.

Abstract: According to one embodiment, a memory system includes nonvolatile memories each storing data and an address table for acquiring an address of the data, and a control unit which is configured to be capable of accessing the nonvolatile memories in parallel, and issues table read requests for reading the address tables and data read requests for reading the data to the nonvolatile memories in response to read commands from a host. When a table read request and a data read request are issued to a same nonvolatile memory, the control unit processes the data read request in priority to the table read request.

Abstract: According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data.

Abstract: A memory device according to an embodiment includes a non-volatile storage device from which data is read and to which data is written, an interface that is connected to the host device by a multiple upstream lanes and/or a multiple downstream lanes and performs data communication in both directions with the host device, and a memory controller. The memory controller changes a connection state of each lane on the basis of lane settings which are determined on the basis of at least one of an amount of data transmitted and the sequentiality of data when the data is transmitted between the memory device and the host device.

Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

Abstract: According to one embodiment, an information processing device includes an OS and a virtual machine switching section. The OS accesses a hardware resource including a nonvolatile semiconductor memory and a semiconductor memory used as a cache memory of the nonvolatile semiconductor memory. The virtual machine switching section switches a virtual machine in exection from a first virtual machine to a second virtual machine while a cache process is executed, when cache miss in a process executed by the first virtual machine is detected.

Abstract: According to one embodiment, an information processing device includes a first determination section and a setting section. The first determination section determines inconsistency between first data and second data. The first data is stored in a nonvolatile semiconductor memory. The second data is corresponding to the first data and stored in a semiconductor memory. The setting section sets execution timing of write back based on access frequency information associated with the second data.

Abstract: According to one embodiment, a memory device is connectable to a host device. The memory device includes a first interface unit, a controller unit, a second memory and a second interface. The first interface unit receives a write command from the host device. The controller unit acquires the write-data associated with the write command stored in a first memory area of a first memory in the host device, the write-data being copied from a second memory area of the first memory. The second interface causes the second memory to write the write-data in the second memory.