Patents by Inventor Atsushi Kunimatsu

Atsushi Kunimatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160054938
    Abstract: According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data.
    Type: Application
    Filed: November 2, 2015
    Publication date: February 25, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsutomu OWA, Masaki MIYAGAWA, Atsushi KUNIMATSU, Mari TAKADA
  • Patent number: 9268706
    Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: February 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Kunimatsu, Kenichi Maeda
  • Patent number: 9235507
    Abstract: According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: January 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsutomu Owa, Masaki Miyagawa, Atsushi Kunimatsu, Mari Takada
  • Publication number: 20150058541
    Abstract: According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data.
    Type: Application
    Filed: October 3, 2014
    Publication date: February 26, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsutomu OWA, Masaki MIYAGAWA, Atsushi KUNIMATSU, Mari TAKADA
  • Publication number: 20150039808
    Abstract: According to one embodiment, a memory system includes nonvolatile memories each storing data and an address table for acquiring an address of the data, and a control unit which is configured to be capable of accessing the nonvolatile memories in parallel, and issues table read requests for reading the address tables and data read requests for reading the data to the nonvolatile memories in response to read commands from a host. When a table read request and a data read request are issued to a same nonvolatile memory, the control unit processes the data read request in priority to the table read request.
    Type: Application
    Filed: December 17, 2013
    Publication date: February 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Kaburaki, Atsushi Kunimatsu
  • Patent number: 8880836
    Abstract: According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Owa, Masaki Miyagawa, Atsushi Kunimatsu, Mari Takada
  • Publication number: 20140244904
    Abstract: A memory device according to an embodiment includes a non-volatile storage device from which data is read and to which data is written, an interface that is connected to the host device by a multiple upstream lanes and/or a multiple downstream lanes and performs data communication in both directions with the host device, and a memory controller. The memory controller changes a connection state of each lane on the basis of lane settings which are determined on the basis of at least one of an amount of data transmitted and the sequentiality of data when the data is transmitted between the memory device and the host device.
    Type: Application
    Filed: August 2, 2013
    Publication date: August 28, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro KONDO, Atsushi Kunimatsu, Atsushi Shiraishi
  • Patent number: 8738851
    Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kunimatsu, Hiroto Nakai, Hiroyuki Sakamoto, Kenichi Maeda
  • Patent number: 8645612
    Abstract: According to one embodiment, an information processing device includes an OS and a virtual machine switching section. The OS accesses a hardware resource including a nonvolatile semiconductor memory and a semiconductor memory used as a cache memory of the nonvolatile semiconductor memory. The virtual machine switching section switches a virtual machine in exection from a first virtual machine to a second virtual machine while a cache process is executed, when cache miss in a process executed by the first virtual machine is detected.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: February 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kunimatsu, Goh Uemura, Tsutomu Owa
  • Patent number: 8612692
    Abstract: According to one embodiment, an information processing device includes a first determination section and a setting section. The first determination section determines inconsistency between first data and second data. The first data is stored in a nonvolatile semiconductor memory. The second data is corresponding to the first data and stored in a semiconductor memory. The setting section sets execution timing of write back based on access frequency information associated with the second data.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenta Yasufuku, Masaki Miyagawa, Goh Uemura, Tsutomu Owa, Tsutomu Unesaki, Atsushi Kunimatsu
  • Publication number: 20130290647
    Abstract: According to one embodiment, a memory device is connectable to a host device. The memory device includes a first interface unit, a controller unit, a second memory and a second interface. The first interface unit receives a write command from the host device. The controller unit acquires the write-data associated with the write command stored in a first memory area of a first memory in the host device, the write-data being copied from a second memory area of the first memory. The second interface causes the second memory to write the write-data in the second memory.
    Type: Application
    Filed: February 4, 2013
    Publication date: October 31, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Maeda, Nobuhiro Kondo, Atsushi Kunimatsu
  • Publication number: 20130254471
    Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.
    Type: Application
    Filed: May 9, 2013
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kunimatsu, Hiroto Nakai, Hiroyuki Sakamoto, Kenichi Maeda
  • Publication number: 20130198437
    Abstract: In an embodiment, a device includes a first unit, a second unit, and a third unit. The first unit generates a write address representing a write position to sequentially store sequential data from a processor to a nonvolatile main memory. The second unit generates order information representing a degree of newness of write. The third unit writes sequentially writes the sequential data at the write address with the order information.
    Type: Application
    Filed: July 27, 2012
    Publication date: August 1, 2013
    Inventors: Takashi OMIZO, Tsutomu OWA, Atsushi KUNIMATSU, Hiroto NAKAI, Masaki MIYAGAWA, Reina NISHINO, Hiroyuki SAKAMOTO
  • Publication number: 20130198445
    Abstract: According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory stores data pieces and search information including entries, where each entry is associated with a search key for specifying one data piece and a real address at which the data piece is stored. Upon reception of a first command, the controller, when the first command specifies a search key, outputs one data piece corresponding to one entry which includes the search key, and when the first command specifies one real address, outputs one data piece corresponding to one entry including the real address.
    Type: Application
    Filed: July 25, 2012
    Publication date: August 1, 2013
    Inventors: Yosuke BANDO, Atsuhiro KINOSHITA, Atsushi KUNIMATSU
  • Publication number: 20130191609
    Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
    Type: Application
    Filed: July 30, 2012
    Publication date: July 25, 2013
    Inventors: Atsushi KUNIMATSU, Kenichi MAEDA
  • Patent number: 8458436
    Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: June 4, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kunimatsu, Hiroto Nakai, Hiroyuki Sakamoto, Kenichi Maeda
  • Patent number: 8261041
    Abstract: An example of a device comprises a first MMU converting a logical address into a physical address for a cache, a controller accessing the cache based on the physical address for the cache, a first storage storing history data showing an access state to a main memory outside a processor, a second storage storing relation data showing a relationship between a logical address and a physical address in the main memory, and a second MMU converting a logical address into a physical address for the main memory based on the history and relation data and accessing the main memory based on the physical address for the main memory. The first and second MMU, controller, first storage, second storage are included in the processor.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: September 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Atsushi Kunimatsu
  • Patent number: 8255614
    Abstract: An information processing device of an example of the invention comprises an address generation section that generates a write address indicating a write position in a nonvolatile memory so that the write position is shifted in order to suppress each number of times of overlapped writing for each position of the nonvolatile memory when a write operation to the nonvolatile memory from a processor is performed, an order generation section that generates order information indicating a generation order of the writing operation, and a write control section that stores write information to the write address, and stores the order information to the nonvolatile memory so that the order information is related to at least one of the stored write information and the write address.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: August 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Omizo, Atsushi Kunimatsu
  • Publication number: 20120191900
    Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.
    Type: Application
    Filed: January 17, 2012
    Publication date: July 26, 2012
    Inventors: Atsushi KUNIMATSU, Masaki MIYAGAWA, Hiroshi NOZUE, Kazuhiro KAWAGOME, Hiroto NAKAI, Hiroyuki SAKAMOTO, Tsutomu OWA, Tsutomu UNESAKI, Reina NISHINO, Kenichi MAEDA, Mari TAKADA
  • Publication number: 20120124290
    Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.
    Type: Application
    Filed: January 30, 2012
    Publication date: May 17, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kunimatsu, Hiroto Nakai, Hiroyuki Sakamoto, Kenichi Maeda