Patents by Inventor Atsushi Kunimatsu

Atsushi Kunimatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7237072
    Abstract: A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: June 26, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Mori, Atsushi Kunimatsu
  • Patent number: 7233998
    Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: June 19, 2007
    Assignees: Sony Computer Entertainment Inc., Kabushiki Kaisha Toshiba, International Business Machines Corporation
    Inventors: Masakazu Suzuoki, Takeshi Yamazaki, Harm Peter Hofstee, Martin E. Hopkins, Charles Ray Johns, James Allan Kahle, Shigehiro Asano, Atsushi Kunimatsu
  • Publication number: 20060155906
    Abstract: A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.
    Type: Application
    Filed: March 14, 2006
    Publication date: July 13, 2006
    Inventors: Kenichi Mori, Atsushi Kunimatsu
  • Patent number: 7042448
    Abstract: The present invention provides an image processing unit, an image processing system, and an image processing method capable of achieving a higher speed and a higher efficiency in a rendering and implementing a low cost of the system. The image processing unit according to the present invention comprises a main storing portion for storing information of three-dimensional objects, a plurality of calculating portions for processing images based on three-dimensional object information which are read from the main storing portion, and a hierarchical storing portion having a plurality of hierarchies and connected between the main storing portion and the plurality of calculating portions to store a part of information at a lower level into a higher level sequentially, wherein image processing by the plurality of calculating portions are performed in parallel.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: May 9, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kunimatsu, Kiyoji Ueno, Hideki Yasukawa, Yukio Watanabe, Takayuki Kamei, Takanao Amatsubo
  • Patent number: 7035982
    Abstract: A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: April 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Mori, Atsushi Kunimatsu
  • Publication number: 20060020771
    Abstract: In a multiprocessor system of a hierarchy configuration as a parallel computer of a common-bus structure, a processing unit (120) in an intermediate stage has a processor (123) having a programmable function that is equal to a normal processor, an instruction memory (125), and a data memory (127). The processing unit (120) receives a status signal from a lower processor (143), and a DMA controller (151) having a memory for the transfer of large sized data performs compression, decompression, programmable load dispersion, and load dispersion according to the state of operation of each lower processor.
    Type: Application
    Filed: September 26, 2005
    Publication date: January 26, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kunimatsu, Yukio Watanabe, Hideki Yasukawa
  • Publication number: 20050275658
    Abstract: A secondary texture cache is used commonly by a plurality of texture units, and stores part of texture data in a main memory. A cache controlling CPU controls a refill operation from the main memory to the secondary texture cache in accordance with cache misses of the plurality of texture units, so as to suppress occurrence of thrashing in the secondary texture cache. The cache controlling CPU suppresses occurrence of the refill operation when the plurality of operating units access an identical memory address with a predetermined time difference.
    Type: Application
    Filed: May 31, 2005
    Publication date: December 15, 2005
    Inventors: Nobuo Sasaki, Takeshi Yamazaki, Atsushi Kunimatsu, Hideki Yasukawa
  • Patent number: 6940519
    Abstract: A graphics processor includes a shading processing section which subjects pixel data to a shading process, a first path which permits map data and texture data output from a video memory to be input to the shading processing section, a second path which permits pixel data output from the shading processing section to be output to the video memory, and a third path which permits pixel data output from a pixel expanding section to be input to the shading processing section. Further, the third path permits pixel data output from the video memory to be input to the shading processing section instead of the pixel data output from the pixel expanding section.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: September 6, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Saito, Atsushi Kunimatsu
  • Patent number: 6938149
    Abstract: A renaming apparatus configured to set a correspondence between a physical register number and a logical register number. The apparatus includes a control register configured to store the correspondence between the physical register number and the logical register number and a control register setting part configured to set the control register in accordance with the content of an instruction, when an instruction for setting the correspondence between the physical register number and the logical register number is included in the issued string of instructions.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: August 30, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kunimatsu, Yukio Watanabe
  • Publication number: 20050174348
    Abstract: Disclosed is an image processing apparatus, comprising a shading-information acquisition device 1 for picking up an image of an actual sample, a shading-information calculation section 201 for calculating shading information using the image acquired by the shading-information acquisition device 1, and storing the calculated shading information in a shading-information storage section 101, in association with the value of a parameter including an image pickup condition during the pickup of the image, a parameter calculation section 203 for calculating a specific value of the parameter at given position of a virtual 3-dimensional model, a shading-information read section 204 for allowing the shading-information storage section 101 to read the shading information corresponding to the calculated parameter value therethrough, and a shading processing section 206 for calculating a brightness value at a target position HP of the virtual 3-dimensional model, using the read shading information and a texture stored in
    Type: Application
    Filed: October 29, 2003
    Publication date: August 11, 2005
    Inventors: Yoshiyuki Sakaguchi, Shintaro Takemura, Shigeru Mitsui, Yasunobu Yamauchi, Atsushi Kunimatsu
  • Patent number: 6809734
    Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: October 26, 2004
    Assignees: Sony Computer Entertainment Inc., Kabushiki Kaisha Toshiba, International Business Machines Corporation
    Inventors: Masakazu Suzuoki, Takeshi Yamazaki, Charles Ray Johns, Shigehiro Asano, Atsushi Kunimatsu, Yukio Watanabe
  • Patent number: 6809422
    Abstract: A block expanding section and a plurality of pixel processing sections are formed in the same semiconductor chip. The block expanding section handles an area to be drawn in units of blocks each composed of an appropriate number of pixels and performs expansion calculation of information of a representative value of each block. Each of the plurality of pixel processing sections has a pixel expanding section and a computing section. The pixel expanding section expands information in units of pixels at least in a rectangular area from block representative point information calculated in the block expanding section. The computing section performs computation in units of pixels information-expanded by the pixel expanding section. Each of the plurality of pixel processing sections selectively performs either graphics processing performed in cooperation with the block expanding section, or image processing performed independent of the block expanding section.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: October 26, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Saito, Kenichi Mori, Atsushi Kunimatsu
  • Publication number: 20040207624
    Abstract: A graphics processor includes a shading processing section which subjects pixel data to a shading process, a first path which permits map data and texture data output from a video memory to be input to the shading processing section, a second path which permits pixel data output from the shading processing section to be output to the video memory, and a third path which permits pixel data output from a pixel expanding section to be input to the shading processing section. Further, the third path permits pixel data output from the video memory to be input to the shading processing section instead of the pixel data output from the pixel expanding section.
    Type: Application
    Filed: July 16, 2003
    Publication date: October 21, 2004
    Inventors: Takahiro Saito, Atsushi Kunimatsu
  • Publication number: 20040178507
    Abstract: A block expanding section and a plurality of pixel processing sections are formed in the same semiconductor chip. The block expanding section handles an area to be drawn in units of blocks each composed of an appropriate number of pixels and performs expansion calculation of information of a representative value of each block. Each of the plurality of pixel processing sections has a pixel expanding section and a computing section. The pixel expanding section expands information in units of pixels at least in a rectangular area from block representative point information calculated in the block expanding section. The computing section performs computation in units of pixels information-expanded by the pixel expanding section. Each of the plurality of pixel processing sections selectively performs either graphics processing performed in cooperation with the block expanding section, or image processing performed independent of the block expanding section.
    Type: Application
    Filed: July 21, 2003
    Publication date: September 16, 2004
    Inventors: Takahiro Saito, Kenichi Mori, Atsushi Kunimatsu
  • Publication number: 20040163132
    Abstract: An entertainment device includes a general-purpose signal processor 103 made up of an assembly of component-processors 103A to 103D each of which can operate in parallel under operating environments independent of others component-processors. A management processor 101 controls a cross bar 104 so as to change the operating environments of the respective component-processors 103A to 103D in accordance with a demand for signal processing which is given from a CPU 11, and to change over any one of the component-processors which receives a signal to be processed which is inputted through the cross bar 104 or outputs a processed signal in accordance with the demand for signal processing.
    Type: Application
    Filed: December 11, 2003
    Publication date: August 19, 2004
    Inventors: Masaaki Oka, Akio Ohba, Junichi Asano, Junichi Naoi, Atsushi Kunimatsu, Jiro Amemiya
  • Publication number: 20030177288
    Abstract: A multiprocessor system according to the present invention, comprises a plurality of calculation processors which execute tasks by using data stored in a memory; and a control processor which controls execution of the tasks by said calculation processors; wherein said control processor includes: a dependency relation checking part which checks a dependency relation between a plurality of data when executing the tasks; and a scheduling part which performs access to said memory, data transfer from said memory to said calculation processor, and calculation scheduling in said calculation processors.
    Type: Application
    Filed: May 10, 2002
    Publication date: September 18, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Kunimatsu, Takashi Fujiwara, Jiro Amemiya, Kenji Shirakawa
  • Publication number: 20030174132
    Abstract: The present invention provides an image processing unit, an image processing system, and an image processing method capable of achieving a higher speed and a higher efficiency in a rendering and implementing a low cost of the system. The image processing unit according to the present invention comprises a main storing portion for storing information of three-dimensional objects, a plurality of calculating portions for processing images based on three-dimensional object information which are read from the main storing portion, and a hierarchical storing portion having a plurality of hierarchies and connected between the main storing portion and the plurality of calculating portions to store a part of information at a lower level into a higher level sequentially, wherein image processing by the plurality of calculating portions are performed in parallel.
    Type: Application
    Filed: March 17, 2003
    Publication date: September 18, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Kunimatsu, Kiyoji Ueno, Hideki Yasukawa, Yukio Watanabe, Takayuki Kamei, Takanao Amatsubo
  • Patent number: 6587110
    Abstract: The present invention provides an image processing unit, an image processing system, and an image processing method capable of achieving a higher speed and a higher efficiency in a rendering and implementing a low cost of the system. The image processing unit according to the present invention comprises a main storing portion for storing information of three-dimensional objects, a plurality of calculating portions for processing images based on three-dimensional object information which are read from the main storing portion, and a hierarchical storing portion having a plurality of hierarchies and connected between the main storing portion and the plurality of calculating portions to store a part of information at a lower level into a higher level sequentially, wherein image processing by the plurality of calculating portions are performed in parallel.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: July 1, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Kunimatsu, Kiyoji Ueno, Hideki Yasukawa, Yukio Watanabe, Takayuki Kamei, Takanao Amatsubo
  • Publication number: 20030061455
    Abstract: A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.
    Type: Application
    Filed: September 12, 2002
    Publication date: March 27, 2003
    Inventors: Kenichi Mori, Atsushi Kunimatsu
  • Patent number: 6388672
    Abstract: An internal memory section is divided into plural memory blocks. During a period of time, a relevant memory block of the internal memory section is connected to an external memory unit, while another memory block thereof is connected to a data holding section. During a succeeding period of time, the relevant memory block is connected to the data holding section, while the other memory block is connected to the external memory unit. Data exchange between the data holding section and the external memory unit via the internal memory section is performed while the alternative connection is repeated.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: May 14, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Ide, Atsushi Kunimatsu, Maki Ueno