Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

Abstract: An example of a device comprises a first MMU converting a logical address into a physical address for a cache, a controller accessing the cache based on the physical address for the cache, a first storage storing history data showing an access state to a main memory outside a processor, a second storage storing relation data showing a relationship between a logical address and a physical address in the main memory, and a second MMU converting a logical address into a physical address for the main memory based on the history and relation data and accessing the main memory based on the physical address for the main memory. The first and second MMU, controller, first storage, second storage are included in the processor.

Abstract: An electric comic book delivering server delivers translated electric comic book by transmitting original electric comic book data, mask data and translation data to a client terminal via a communication network. The mask data is used to mask a display portion of first language. The translation data is used to superimpose a display portion of second language on the masked display portion of first language. When the electric comic book delivering server obtains mask data and translation data from another client terminal in which the mask data and the translation data have been created, the electric comic book delivering server registers the mask data and the translation data into a database thereof. The comic book delivering server transmits payment demand information to a client whenever the server transmits, to the client, the original electric comic book data, the mask data and the translation data thus registered.

Abstract: An electric comic book delivering server delivers translated electric comic book by transmitting original electric comic book data, mask data and translation data to a client terminal via a communication network. The mask data is used to mask a display portion of first language. The translation data is used to superimpose a display portion of second language on the masked display portion of first language. When the electric comic book delivering server obtains mask data and translation data from another client terminal in which the mask data and the translation data have been created, the electric comic book delivering server registers the mask data and the translation data into a database thereof.

Abstract: A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.

Abstract: A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.

Abstract: A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.

Abstract: The present invention provides an image processing unit, an image processing system, and an image processing method capable of achieving a higher speed and a higher efficiency in a rendering and implementing a low cost of the system. The image processing unit according to the present invention comprises a main storing portion for storing information of three-dimensional objects, a plurality of calculating portions for processing images based on three-dimensional object information which are read from the main storing portion, and a hierarchical storing portion having a plurality of hierarchies and connected between the main storing portion and the plurality of calculating portions to store a part of information at a lower level into a higher level sequentially, wherein image processing by the plurality of calculating portions are performed in parallel.

Abstract: A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.

Abstract: In a multiprocessor system of a hierarchy configuration as a parallel computer of a common-bus structure, a processing unit (120) in an intermediate stage has a processor (123) having a programmable function that is equal to a normal processor, an instruction memory (125), and a data memory (127). The processing unit (120) receives a status signal from a lower processor (143), and a DMA controller (151) having a memory for the transfer of large sized data performs compression, decompression, programmable load dispersion, and load dispersion according to the state of operation of each lower processor.

Abstract: A secondary texture cache is used commonly by a plurality of texture units, and stores part of texture data in a main memory. A cache controlling CPU controls a refill operation from the main memory to the secondary texture cache in accordance with cache misses of the plurality of texture units, so as to suppress occurrence of thrashing in the secondary texture cache. The cache controlling CPU suppresses occurrence of the refill operation when the plurality of operating units access an identical memory address with a predetermined time difference.

Abstract: A graphics processor includes a shading processing section which subjects pixel data to a shading process, a first path which permits map data and texture data output from a video memory to be input to the shading processing section, a second path which permits pixel data output from the shading processing section to be output to the video memory, and a third path which permits pixel data output from a pixel expanding section to be input to the shading processing section. Further, the third path permits pixel data output from the video memory to be input to the shading processing section instead of the pixel data output from the pixel expanding section.

Abstract: A renaming apparatus configured to set a correspondence between a physical register number and a logical register number. The apparatus includes a control register configured to store the correspondence between the physical register number and the logical register number and a control register setting part configured to set the control register in accordance with the content of an instruction, when an instruction for setting the correspondence between the physical register number and the logical register number is included in the issued string of instructions.

Abstract: Disclosed is an image processing apparatus, comprising a shading-information acquisition device 1 for picking up an image of an actual sample, a shading-information calculation section 201 for calculating shading information using the image acquired by the shading-information acquisition device 1, and storing the calculated shading information in a shading-information storage section 101, in association with the value of a parameter including an image pickup condition during the pickup of the image, a parameter calculation section 203 for calculating a specific value of the parameter at given position of a virtual 3-dimensional model, a shading-information read section 204 for allowing the shading-information storage section 101 to read the shading information corresponding to the calculated parameter value therethrough, and a shading processing section 206 for calculating a brightness value at a target position HP of the virtual 3-dimensional model, using the read shading information and a texture stored in

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A block expanding section and a plurality of pixel processing sections are formed in the same semiconductor chip. The block expanding section handles an area to be drawn in units of blocks each composed of an appropriate number of pixels and performs expansion calculation of information of a representative value of each block. Each of the plurality of pixel processing sections has a pixel expanding section and a computing section. The pixel expanding section expands information in units of pixels at least in a rectangular area from block representative point information calculated in the block expanding section. The computing section performs computation in units of pixels information-expanded by the pixel expanding section. Each of the plurality of pixel processing sections selectively performs either graphics processing performed in cooperation with the block expanding section, or image processing performed independent of the block expanding section.