Patents by Inventor Atsushi Miyanishi
Atsushi Miyanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10482949Abstract: A semiconductor device includes a first mode and a second mode different from the first mode, includes a memory circuit including a first switch, a memory array, and a peripheral circuit. A first power source line is electrically coupled with an I/O circuit of the peripheral circuit and is supplied with a first voltage in the first mode. A second power source line is electrically coupled with a memory cell of the memory array, and supplied with a second voltage lower than the first voltage in the second mode.Type: GrantFiled: February 11, 2019Date of Patent: November 19, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
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Patent number: 10360091Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.Type: GrantFiled: October 4, 2018Date of Patent: July 23, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichiro Ishii, Atsushi Miyanishi, Yoshikazu Saito
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Publication number: 20190172524Abstract: A semiconductor device includes a first mode and a second mode different from the first mode, includes a memory circuit including a first switch, a memory array, and a peripheral circuit. A first power source line is electrically coupled with an I/O circuit of the peripheral circuit and is supplied with a first voltage in the first mode. A second power source line is electrically coupled with a memory cell of the memory array, and supplied with a second voltage lower than the first voltage in the second mode.Type: ApplicationFiled: February 11, 2019Publication date: June 6, 2019Inventors: Yuichiro ISHII, Atsushi MIYANISHI, Kazumasa YANAGISAWA
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Patent number: 10224096Abstract: A semiconductor device includes: a first power source line for supplying a first voltage; a second power source line for supplying a second voltage; a memory circuit coupled with the first and second power source lines; a first switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to a control signal; a second switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to the control signal, wherein a memory circuit includes a memory cell array and a peripheral circuit, wherein a memory cell array includes a plurality of memory cells, the memory cells coupled with the second power source line.Type: GrantFiled: March 14, 2018Date of Patent: March 5, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
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Publication number: 20190034260Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.Type: ApplicationFiled: October 4, 2018Publication date: January 31, 2019Inventors: Yuichiro ISHII, Atsushi MIYANISHI, Yoshikazu SAITO
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Patent number: 10120741Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.Type: GrantFiled: September 20, 2017Date of Patent: November 6, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichiro Ishii, Atsushi Miyanishi, Yoshikazu Saito
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Publication number: 20180204612Abstract: A semiconductor device includes: a first power source line for supplying a first voltage; a second power source line for supplying a second voltage; a memory circuit coupled with the first and second power source lines; a first switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to a control signal; a second switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to the control signal, wherein a memory circuit includes a memory cell array and a peripheral circuit, wherein a memory cell array includes a plurality of memory cells, the memory cells coupled with the second power source line.Type: ApplicationFiled: March 14, 2018Publication date: July 19, 2018Inventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
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Patent number: 9959925Abstract: A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in the active mode; a second power source line which accepts the supply of power in the active mode and the standby mode; a memory circuit to be coupled with the first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line.Type: GrantFiled: October 31, 2017Date of Patent: May 1, 2018Assignee: Renesas Electronics CorporationInventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
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Publication number: 20180068712Abstract: A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in the active mode; a second power source line which accepts the supply of power in the active mode and the standby mode; a memory circuit to be coupled with the first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line.Type: ApplicationFiled: October 31, 2017Publication date: March 8, 2018Inventors: Yuichiro ISHII, Atsushi Miyanishi, Kazumasa Yanagisawa
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Publication number: 20180053546Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.Type: ApplicationFiled: October 27, 2017Publication date: February 22, 2018Inventors: Atsushi MIYANISHI, Yuichiro ISHII, Yoshisato YOKOYAMA
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Publication number: 20180018211Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.Type: ApplicationFiled: September 20, 2017Publication date: January 18, 2018Inventors: Yuichiro ISHII, Atsushi MIYANISHI, Yoshikazu SAITO
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Patent number: 9837140Abstract: A semiconductor device including a first N-type well and a second N-type well includes: a memory circuit to be coupled with first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line and electrically decouples the first power source line from the second power source line. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The first and second switches each include a first PMOS transistor arranged in the first N-type well.Type: GrantFiled: December 22, 2016Date of Patent: December 5, 2017Assignee: Renesas Electronics CorporationInventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
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Patent number: 9830980Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.Type: GrantFiled: March 21, 2017Date of Patent: November 28, 2017Assignee: Renesas Electronics CorporationInventors: Atsushi Miyanishi, Yuichiro Ishii, Yoshisato Yokoyama
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Patent number: 9798600Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.Type: GrantFiled: September 28, 2015Date of Patent: October 24, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichiro Ishii, Atsushi Miyanishi, Yoshikazu Saito
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Patent number: 9728272Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.Type: GrantFiled: January 18, 2016Date of Patent: August 8, 2017Assignee: Renesas Electronics CorporationInventors: Atsushi Miyanishi, Yuichiro Ishii, Yoshisato Yokoyama
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Publication number: 20170194049Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.Type: ApplicationFiled: March 21, 2017Publication date: July 6, 2017Inventors: Atsushi MIYANISHI, Yuichiro ISHII, Yoshisato YOKOYAMA
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Publication number: 20170103803Abstract: A semiconductor device including a first N-type well and a second N-type well includes: a memory circuit to be coupled with first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line and electrically decouples the first power source line from the second power source line. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The first and second switches each include a first PMOS transistor arranged in the first N-type well.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Inventors: Yuichiro ISHII, Atsushi MIYANISHI, Kazumasa YANAGISAWA
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Patent number: 9559693Abstract: A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.Type: GrantFiled: September 25, 2015Date of Patent: January 31, 2017Assignee: Renesas Electronics CorporationInventors: Yuichiro Ishii, Atsushi Miyanishi, Kazumasa Yanagisawa
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Publication number: 20160254062Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.Type: ApplicationFiled: January 18, 2016Publication date: September 1, 2016Inventors: Atsushi MIYANISHI, Yuichiro ISHII, Yoshisato YOKOYAMA
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Publication number: 20160126953Abstract: A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.Type: ApplicationFiled: September 25, 2015Publication date: May 5, 2016Inventors: Yuichiro Ishii, Atsushi MIYANISHI, Kazumasa YANAGISAWA