Abstract: In the construction of a P-well area formed with a pair of CMOS inverters and a N-well area that constitute a multi-port SRAM cell, the P-well area is divided into two P-well areas. These two P-well areas are disposed on the two sides of the N-well area. A layout is provided such that the boundaries between the P-well areas and the N-well area are parallel to the bit lines. Two access gates are formed in one P-well area and two access gates are formed in the other P-well area. Thus, the bit lines can be made shorter, and the amount of wiring can be reduced.

Abstract: A pulse generation circuit (11) generates a pulse signal (S11) of “L” with a rise of a clock signal (CLOCK) as a trigger. A latch circuit (12) changes a latch signal (S12) from “L” to “H” on the basis of the pulse signal (11) of “L”. Inverters (G10, G11) output a signal (XDEC) on the basis of the latch signal (S12). Even when the generation of the “L” pulse of the pulse signal (S11) is terminated and the pulse signal (S11) returns to “H”, the latch circuit (12) is in a data holding state to sustain the latch signal (S12) of “H” during a period while the signal READY takes “H”. With this constitution, it is possible to provide a semiconductor integrated circuit having a control unit which can output an operation control signal in synchronization with the clock signal without being constrained by the time length of “H” (“L”) period of the clock signal.

Abstract: In the construction of a P-well area including a pair of CMOS inverters and a N-well area of a multi-port SRAM cell, the P-well area is divided into two P-well areas. These two P-well areas are disposed on two sides of the N-well area. A layout is provided such that the boundaries between the P-well areas and the N-well area are parallel to bit lines. Two access gates are located in one P-well area and two access gates are located in the other P-well area. Thus, the bit lines can be made shorter, and the amount of wiring can be reduced.

Abstract: In the construction of a P-well area formed with a pair of CMOS inverters and a N-well area that constitute a multi-port SRAM cell, the P-well area is divided into two P-well areas. These two P-well areas are disposed on the two sides of the N-well area. A layout is provided such that the boundaries between the P-well areas and the N-well area are parallel to the bit lines. Two access gates are formed in one P-well area and two access gates are formed in the other P-well area. Thus, the bit lines can be made shorter, and the amount of wiring can be reduced.

Abstract: Subbanks are arranged in four regions of a DRAM macro having a rectangular shape, bank control circuits are arranged in a prescribed region between these subbanks, and internal read/write data buses are arranged in a region different from the region where the bank control circuits are arranged. Since there is no crossing of the bank control circuits and the internal read/write data buses, the bank control circuits can be efficiently arranged to reduce the layout area. Accordingly, a semiconductor integrated circuit device including multi-bank memories which operates stably at high speed can be provided without increase of an area occupied by a chip.

Abstract: A DRAM control circuit or a test circuit describing a delay control cell is prepared. Automatic placement and routing is performed in relation to this circuit. Circuit simulation is executed at a step ST16. Delay control is performed with the delay control cell on the basis of a simulation result. Alternatively, delay control is performed with a circuit of the delay control cell on the basis of a test result. Thus, automatic placement and routing of at least either the DRAM control circuit or the test circuit provided in a DRAM is enabled.

Abstract: Normalization circuitry comprises an AND gate for computing the AND of a reference signal generated from an exponent input with a mantissa input, and an OR gate for computing the OR of all the bits of the output of the AND gate. A leading one detector detects the bit position of the leading 1 of the mantissa input, and then generates a signal only one bit at the detected bit position of which is set to 1. A priority encoder then subtracts 1 from the number showing the bit position of the leading 1 counted from the most significant bit (MSB). A one-bit shifter shifts all the bits of the signal except its MSB from the leading one detector one bit position to the right.

Abstract: It is an object to realize in a floating point computation device a normalization circuit device which carries out normalization, unnormalization and 0 function operation at high speed. A circuit (3) outputs 1 from the most significant bit for the number obtained by adding 1 to a decimal number value of the exponent part input signal (A). AND operation of the signal (A") and the mantissa part input signal (B) and OR operation of all bits of the value ((3) provide a control signal (G'). A circuit (2) represents in a binary value (B') a number obtained by subtracting 1 from a number value of the bit position of the leading 1 from the most significant bit of the signal (B). A circuit (6) subtracts the valve (B') from the signal (A) and a circuit (7b) selects the signal (H) and a 0 value according to the signal (G') to obtain an exponent part output signal (C) after normalization.