Patents by Inventor Atsushi Miyanishi
Atsushi Miyanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160092293Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.Type: ApplicationFiled: September 28, 2015Publication date: March 31, 2016Inventors: Yuichiro ISHII, Atsushi MIYANISHI, Yoshikazu SAITO
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Patent number: 8514612Abstract: A semiconductor memory device is provided in which erroneous writing to a dual port memory cell can be prevented without short-circuiting bit lines coupled to two ports. The first write driver applies voltage corresponding to the first write data to the first bit line, when activated. The first write assist driver applies voltage corresponding to the first write data to the second bit line, when activated. A row of the memory cell array for the first access through the first port is specified by the first row address, and a row of the memory cell array for the second access through the second port is specified by the second row address. The first write assist driver is activated at least on condition that the first write driver is activated and that the first row address and the second row address coincide.Type: GrantFiled: May 26, 2011Date of Patent: August 20, 2013Assignee: Renesas Electronics CorporationInventors: Yuichiro Ishii, Atsushi Miyanishi
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Patent number: 8140220Abstract: An object of the invention is to provide an in-vehicle apparatus and an in-vehicle system that can use a plurality of expansion modules. The in-vehicle apparatus includes a plurality of slots for connecting a plurality of modules, each having a connector for connection, to expand capabilities of the in-vehicle apparatus, and a control unit for identifying the kind of each of the plurality of modules connected to the plurality of slots.Type: GrantFiled: May 29, 2009Date of Patent: March 20, 2012Assignee: Fujitsu Ten LimitedInventors: Seiji Fujikawa, Hidenori Kurose, Atsushi Miyanishi, Junji Amaya, Hidehiko Sowa, Kohichi Watanabe, Yasuo Nakashima
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Publication number: 20120017184Abstract: When generating a temporary ROM code file and a design information file, a host server generates a dedicated ROM compiler and an intermediate file associated with the dedicated ROM compiler. In a workstation, the dedicated ROM compiler is executed, whereby the contents of a design information file are changed to the contents corresponding to a correct ROM code. The dedicated ROM compiler is specifically designed to be capable of changing only a particular design parameter and the design information file associated with the temporary ROM code file.Type: ApplicationFiled: April 15, 2009Publication date: January 19, 2012Inventors: Michiko Tsukamoto, Takashi Nakajima, Atsushi Miyanishi
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Publication number: 20110305072Abstract: A semiconductor memory device is provided in which erroneous writing to a dual port memory cell can be prevented without short-circuiting bit lines coupled to two ports. The first write driver applies voltage corresponding to the first write data to the first bit line, when activated. The first write assist driver applies voltage corresponding to the first write data to the second bit line, when activated. A row of the memory cell array for the first access through the first port is specified by the first row address, and a row of the memory cell array for the second access through the second port is specified by the second row address. The first write assist driver is activated at least on condition that the first write driver is activated and that the first row address and the second row address coincide.Type: ApplicationFiled: May 26, 2011Publication date: December 15, 2011Inventors: Yuichiro ISHII, Atsushi Miyanishi
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Publication number: 20110110166Abstract: The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.Type: ApplicationFiled: January 18, 2011Publication date: May 12, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Atsushi MIYANISHI
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Patent number: 7898896Abstract: The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.Type: GrantFiled: March 25, 2009Date of Patent: March 1, 2011Assignee: Renesas Electronics CorporationInventor: Atsushi Miyanishi
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Publication number: 20090299572Abstract: An object of the invention is to provide an in-vehicle apparatus and an in-vehicle system that can use a plurality of expansion modules. The in-vehicle apparatus includes a plurality of slots for connecting a plurality of modules, each having a connector for connection, to expand capabilities of the in-vehicle apparatus, and a control unit for identifying the kind of each of the plurality of modules connected to the plurality of slots.Type: ApplicationFiled: May 29, 2009Publication date: December 3, 2009Applicant: FUJITSU TEN LIMITEDInventors: Seiji Fujikawa, Hidenori Kurose, Atsushi Miyanishi, Junji Amaya, Hidehiko Sowa, Kohichi Watanabe, Yasuo Nakashima
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Publication number: 20090185431Abstract: The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.Type: ApplicationFiled: March 25, 2009Publication date: July 23, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventor: Atsushi Miyanishi
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Publication number: 20070168773Abstract: A semiconductor memory unit with a repair circuit includes a controller, a 2-to-1 selector, an address decoder and an address comparator. The controller supplies the 2-to-1 selector and the address comparator with a setup signal to carry out the following control. When the 2-to-1 selector is controlled to supply the address decoder with a repair address signal, the address comparator is controlled to have a repair signal information holding section, which is installed in the address comparator, hold the repair address decoded by the address decoder. When the 2-to-1 selector is controlled to supply the address decoder with a read/write address signal, the address comparator is controlled to compare the read/write address with the repair address. The semiconductor memory unit can obviate the need for a repair address decoder, thereby reducing the unit area.Type: ApplicationFiled: March 1, 2007Publication date: July 19, 2007Inventor: Atsushi Miyanishi
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Patent number: 7203870Abstract: A semiconductor memory unit with a repair circuit includes a controller, a 2-to-1 selector, an address decoder and an address comparator. The controller supplies the 2-to-1 selector and the address comparator with a setup signal to carry out the following control. When the 2-to-1 selector is controlled to supply the address decoder with a repair address signal, the address comparator is controlled to have a repair signal information holding section, which is installed in the address comparator, hold the repair address decoded by the address decoder. When the 2-to-1 selector is controlled to supply the address decoder with a read/write address signal, the address comparator is controlled to compare the read/write address with the repair address. The semiconductor memory unit can obviate the need for a repair address decoder, thereby reducing the unit area.Type: GrantFiled: December 30, 2002Date of Patent: April 10, 2007Assignee: Renesas Technology Corp.Inventor: Atsushi Miyanishi
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Publication number: 20070047283Abstract: The present invention provides a technique capable of simplifying a layout structure of a semiconductor device having a semiconductor memory section in which an input port and an output port are separated from each other, and which includes a bypass function. In a semiconductor memory device to be used as a semiconductor memory section of the semiconductor device, in a bypass mode, an output buffer outputs input data transmitted through a bypass line, extending from an input buffer circuit to the output buffer circuit, to an output port. In the layout structure of the semiconductor memory device, in plan view, a memory cell array is arranged between the input buffer circuit and the output buffer circuit, and a bypass line is arranged through between the memory cell arrays.Type: ApplicationFiled: August 23, 2006Publication date: March 1, 2007Inventor: Atsushi Miyanishi
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Publication number: 20060271897Abstract: An active area (1) is provided with a concave part in its corner portion in a shape along a plan view. An insulating film (7) encloses this active area. A gate electrode (30) is arranged on a depressed region (DR) having an edge portion which is located on a low position due to the concave part, while a gate electrode (20) is arranged on an ordinary region (OR) having an edge portion projecting beyond the depressed region. A gate end cap (margin part) of the gate electrode (20) has a length x, while that of the gate electrode (30) has a length x+?. Thus provided is a semiconductor device causing no current defect between source/drain regions even if the active area and an insulating film defining this active area fail to satisfy the layout design following refinement of the semiconductor device.Type: ApplicationFiled: July 27, 2006Publication date: November 30, 2006Inventors: Atsushi Miyanishi, Hisashi Matsumoto
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Publication number: 20060271896Abstract: An active area (1) is provided with a concave part in its corner portion in a shape along a plan view. An insulating film (7) encloses this active area. A gate electrode (30) is arranged on a depressed region (DR) having an edge portion which is located on a low position due to the concave part, while a gate electrode (20) is arranged on an ordinary region (OR) having an edge portion projecting beyond the depressed region. A gate end cap (margin part) of the gate electrode (20) has a length x, while that of the gate electrode (30) has a length x+?. Thus provided is a semiconductor device causing no current defect between source/drain regions even if the active area and an insulating film defining this active area fail to satisfy the layout design following refinement of the semiconductor device.Type: ApplicationFiled: July 27, 2006Publication date: November 30, 2006Inventors: Atsushi Miyanishi, Hisashi Matsumoto
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Patent number: 7105901Abstract: An active area (1) is provided with a concave part in its corner portion in a shape along a plan view. An insulating film (7) encloses this active area. A gate electrode (30) is arranged on a depressed region (DR) having an edge portion which is located on a low position due to the concave part, while a gate electrode (20) is arranged on an ordinary region (OR) having an edge portion projecting beyond the depressed region. A gate end cap (margin part) of the gate electrode (20) has a length x, while that of the gate electrode (30) has a length x+?. Thus provided is a semiconductor device causing no current defect between source/drain regions even if the active area and an insulating film defining this active area fail to satisfy the layout design following refinement of the semiconductor device.Type: GrantFiled: July 13, 1998Date of Patent: September 12, 2006Assignee: Renesas Technology Corp.Inventors: Atsushi Miyanishi, Hisashi Matsumoto
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Publication number: 20040078701Abstract: A semiconductor memory unit with a repair circuit includes a controller, a 2-to-1 selector, an address decoder and an address comparator. The controller supplies the 2-to-1 selector and the address comparator with a setup signal to carry out the following control. When the 2-to-1 selector is controlled to supply the address decoder with a repair address signal, the address comparator is controlled to have a repair signal information holding section, which is installed in the address comparator, hold the repair address decoded by the address decoder. When the 2-to-1 selector is controlled to supply the address decoder with a read/write address signal, the address comparator is controlled to compare the read/write address with the repair address. The semiconductor memory unit can obviate the need for a repair address decoder, thereby reducing the unit area.Type: ApplicationFiled: December 30, 2002Publication date: April 22, 2004Inventor: Atsushi Miyanishi
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Patent number: 6535453Abstract: In the construction of a P-well area including a pair of CMOS inverters and a N-well area of a multi-port SRAM cell, the P-well area is divided into two P-well areas. These two P-well areas are disposed on two sides of the N-well area. A layout is provided such that the boundaries between the P-well areas and the N-well area are parallel to bit lines. Two access gates are located in one P-well area and two access gates are located in the other P-well area. Thus, the bit lines can be made shorter, and the amount of wiring can be reduced.Type: GrantFiled: January 28, 2002Date of Patent: March 18, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Koji Nii, Atsushi Miyanishi
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Patent number: 6515920Abstract: A memory core of a semiconductor data storing circuit device in a semiconductor chip is composed of a memory cell array having memory cells of rows and columns, data input/output circuits of a normal operation in which a data input line and a data output line for one bit of data are arranged at every four columns of the memory cell array, and checking circuits of a test operation in which a test data input line and a test data output line for one bit of test data are arranged at every eight (or two) columns of the memory cell array. In cases where the test data input/output lines for one bit of test data are arranged at every eight columns, because the number of test data input/output lines is lower than the number of data input/output lines, the number of input/output pins for the test operation can be reduced.Type: GrantFiled: October 5, 2001Date of Patent: February 4, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hirofumi Nakano, Atsushi Miyanishi, Sizuo Morizane
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Patent number: 6498765Abstract: A pulse generation circuit (11) generates a pulse signal (S11) of “L” with a rise of a clock signal (CLOCK) as a trigger. A latch circuit (12) changes a latch signal (S12) fry “L” to “H” on the basis of the pulse signal (11) of “L”. Inverters (G10, G11) output a signal (XDEC) on the basis of the latch signal (S12). Even when the generation of the “L” pulse of the pulse signal (S11) is terminated and the pulse signal (S11) returns to “H”, the latch circuit (12) is in a data holding state to sustain the latch signal (S12) of “H” during a period while the signal READY takes “H”. With this constitution, it is possible to provide a semiconductor integrated circuit having a control unit which can output an operation control signal in synchronization with the clock signal without being constrained by the time length of “H” (“L”) period of the clock signal.Type: GrantFiled: April 20, 2001Date of Patent: December 24, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yuichiro Ishii, Atsushi Miyanishi, Yoshiyuki Ota
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Publication number: 20020110027Abstract: A memory core of a semiconductor data storing circuit device in a semiconductor chip is composed of a memory cell array having memory cells of rows and columns, data input/output circuits of a normal operation in which a data input line and a data output line for one bit of data are arranged at every four columns of the memory cell array, and checking circuits of a test operation in which a test data input line and a test data output line for one bit of test data are arranged at every eight (or two) columns of the memory cell array. In cases where the test data input/output lines for one bit of test data are arranged at every eight columns, because the number of test data input/output lines is lower than the number of data input/output lines, the number of input/output pins for the test operation can be reduced.Type: ApplicationFiled: October 5, 2001Publication date: August 15, 2002Inventors: Hirofumi Nakano, Atsushi Miyanishi, Sizuo Morizane