Abstract: The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit 110 holds data having been read out of memory cells in a memory cell array 106 designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1 included in the address, a multiplexer 111 sequentially and non-synchronously feeds out the data held in the data latch circuit 110 based on the column addresses A0, A1.

Abstract: The present invention provides a novel method for electrical connection between a polymer PTC device and a metal lead element to thereby prevent the problems of the connection by caulking or soldering. For this purpose, the present invention provides a process for producing a connection structure by laser welding, said connection structure having (A) a PTC device (10) including (i) a laminar polymer PTC element (12) and (ii) a metal foil electrode (14) disposed on a main surface of the laminar polymer PTC element (12), and (B) a metal lead element (20) electrically connected to the metal foil electrode. The metal foil electrode (14) has at least two metal layers, one of which, the X-th layer, has laser beam absorption a % that is the lowest among the metal layers of the metal foil electrode (14). The X-th layer is present between a first metal layer (18) of the metal foil electrode-and the laminar polymer PTC element (12).

Abstract: There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes “H” level, a latch signal La outputted from a latch (11) becomes “H” level, whereby NFETs (14, 17, 24) turn ON. A voltage dividing circuit comprising resistances (12, 13) and current mirror differential amplifiers (20, 27) are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref2, a voltage V2 becomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch (11) is made through. At this time, the signal PL is “L”, the latch signal La outputted from the latch (11) becomes “L”, whereby the NFETs (14, 7, 24) turn OFF.

Abstract: Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.

Abstract: Disclosed is a semiconductor memory device having memory cells that are in need of refresh for data retention, includes control circuits for necessarily generating the refresh immediately before the read/write operation, and for setting the latency to a first fixed value at all times, for the first mode during the testing, and for necessarily generating the refresh immediately after the read/write operation, and for setting the latency to a second fixed value at all times, for the second mode during the testing.

Abstract: There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes “H” level, a latch signal La outputted from a latch becomes “H” level, whereby NFETs turn ON. A voltage dividing circuit comprising resistances and current mirror differential amplifiers are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage). As the boost voltage Vbt is increased and reaches to a reference voltage Vref2, a voltage V2 becomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch is made through. At this time, the signal PL is “L”, the latch signal La outputted from the latch becomes “L”, whereby the NFETs turn OFF. As described here, the NFETs is kept OFF in the other time period than when needed, in order to reduce the power consumption.

Abstract: A method for producing an optically active compound comprising: a first step of culturing a microorganism capable of assimilating either the R-isomer or the S-isomer of a compound represented by Formula (1): wherein R is a methyl, ethyl, propyl, chloromethyl, or hydroxyethyl group, in a culture medium whose Ca2+ concentration at the beginning of culturing is controlled and which contains a racemic mixture of the compound as a carbon source; and a second step of recovering the optically active compound remaining in the culture broth.

Abstract: A nitride semiconductor device including an ohmic electrode with low contact resistance and manufacturing method thereof including a first nitride semiconductor layer made of a III-V group nitride semiconductor layer deposited on a substrate, a second nitride semiconductor layer including the III-V group nitride semiconductor layer whose film formation temperature is lower than that of the first nitride semiconductor layer and being deposited on the first nitride semiconductor layer and not including aluminum. An ohmic electrode is then formed through forming a metal pattern making ohmic contact on the second nitride semiconductor layer being unprocessed crystallinity with minute grains, and then heat treating the metal pattern.

Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Abstract: A nitride semiconductor device enabiling to supress current collapse and manufacturing method thereof including a III-V group nitride semiconductor layer formed of III group elements includes at least one element from the group consisting of gallium, aluminum, boron and indium, and V group elements including at least nitrogen from the group consisting of nitrogen, phosphorous and arsenic, comprising a first nitride semiconductor layer made of said III-V group nitride semiconductor layer deposited on a substrate, a second nitride semiconductor layer comprising said III-V group nitride semiconductor layer and a control electrode making Schottky contact with the first nitride semiconductor layer being exposed through removing a portion of the second semiconductor layer.

Abstract: A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors 3C, 4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit 3 and a boost circuit 4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit 3 and the boost circuit 4.

Abstract: A semiconductor memory device is provided, which is capable of effectively reducing a current comsumption caused by a self-refresh operation in a stand-by mode. In the refresh operation in the stand-by mode, under the control by a refresh control circuit 8B, firstly, a suppression is made for current driving abilities of sense amplifiers 70A˜70D provided for amplifying data signals appearing on bit lines, and secondly, an expansion is made of a pulse width of a row enable signal RE, which defines a period of time for selecting word lines WL, and thirdly, parallel activations of plural word lines are made based on the row enable signal RE with the expanded pulse width, thereby reducing the frequency of operations of the circuit system associated with the refresh operations, resulting in a suppression of the current consumption.

Abstract: A power tool includes: a stator having a substantially cylindrical yoke and a plurality of permanent magnets that are firmly fixed to an inner surface of the yoke and circumferentially spaced from each other by a first gap; a rotor inserted inside the permanent magnets at a second gap radially; an outer frame portion that accommodates the stator and the rotor; a ventilation hole formed in the outer frame portion to place the first and second gaps in communication with an atmosphere; and a dustproof member comprising a ferromagnetic material, which is mounted in contact with the stator and has a protruding portion located in a passage going from the first and second gaps to the atmosphere via the ventilation hole.

Abstract: A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S0, S1 are divided into respective four blocks B0˜B3 and B10˜B13. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.

Abstract: A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit (4) receives change of an address (“Address”), and generates a one shot pulse in an address transition detect signal (ATD) after an address skew period has elapsed. In the case of a write request, a write enable signal (/WE) is dropped within the address skew period. First, writing or reading is performed from the rising edge of the one shot pulse, and, in the case of writing, late writing is performed using the address and the data which were presented at the time of the directly preceding write request. Next, refresh is performed during the period from the falling edge of the one shot pulse until the address skew period of the subsequent memory cycle is completed.

Abstract: A reader/writer of a wireless communication device transmits a carrier signal from an antenna, and if there is not response from an IC card within a preset time after transmitting the polling command, the carrier signal is temporarily controlled to an OFF state.

Abstract: A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors 3C, 4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit 3 and a boost circuit 4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit 3 and the boost circuit 4.

Abstract: The present invention provides a method for obtaining optically active 3-chloro-2-methyl-1,2-propanediol, the method comprising: a first step of letting at least one kind of microorganism or processed product thereof having an ability to leave untouched (R)-3-chloro-2-methyl-1,2-propanediol or (S)-3-chloro-2-methyl-1,2-propanediol in the presence of an enantiomeric 3-chloro-2-methyl-1,2-propanediol mixture act on an enantiomeric 3-chloro-2-methyl-1,2-propanediol mixture; and a second step of recovering the untouched optically active 3-chloro-2-methyl-1,2-propanediol.

Abstract: A nitride semiconductor device, which includes a III-V Group nitride semiconductor layer being composed of a III Group element consisting of at least one of a group containing of gallium, aluminum, boron and indium and V Group element consisting of at least nitrogen among a group consisting of nitrogen, phosphorus and arsenic, including a first nitride semiconductor layer including the III-V Group nitride semiconductor layer being deposited on a substrate, a second nitride semiconductor layer including the III-V Group nitride semiconductor layer being deposited on the first nitride semiconductor and not containing aluminum and a control electrode making Schottky contact with the second nitride semiconductor layer wherein the second nitride semiconductor layer includes a film whose film forming temperature is lower than the first nitride semiconductor layer.

Abstract: The semiconductor device includes a reference voltage generator circuit and a circuit different from the reference voltage generator circuit. A semiconductor element of the reference voltage generator circuit has a channel region where a substrate impurity concentration is substantially uniform at least in the vicinity of a drain region. A semiconductor element of the circuit different from the reference voltage generator circuit has a channel region where a substrate impurity concentration is higher than in other part of the region at least in the drain region.