Abstract: An operation control circuit is provided for shortening a transition time from a deep stand-by mode to a stand-by mode in a pseudo-SRAM having the deep stand-by mode and the stand-by mode. The transition from the deep stand-by mode to the stand-by mode starts first and second timer circuits which respectively output a timer output TN of a constant cycle needed for self-refresh and a timing signal TR of a shorter cycle than a self-refresh cycle. A counter circuit counts the output TR from the second timer circuit immediately after the deep stand-by mode has been transitioned to the stand-by mode. If the counted value corresponds to a value as set, then the counter circuit outputs an operation mode switching signal. A selector circuit comprising a multiplexer is switched and controlled by the output from the counter circuit.

Abstract: A semiconductor memory device capable of accelerating address access and shortening cycle time is provided. A first address decoder (2) and first refresh address decoder (5) respectively decode an external address (Xn) supplied from outside the semiconductor memory device and a refresh address (RXn) used for refreshing within the semiconductor memory device. A multiplexer (8) selects the external address side decode signal (XnDm) or the refresh address side decode signal (XnRm) and outputs the signal as a decode signal (XnMm) based on an external address transmission signal (EXTR) and refresh address transmission signal (RFTR) so that a refresh operation and a read/write operation is performed continuously within one memory cycle. A word driver (10) then decodes decode signals (XnMm, XpMq) selected with multiplexer (8) and so forth, and activates a word line (WLmq).

Abstract: Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.

Abstract: It is an object to provide a timer circuit which exhibits a tendency of decreasing a timer cycle upon a temperature increase and another tendency of increasing the timer cycle upon a temperature decrease. A diode D has a current characteristic depending upon temperature. A forward current flows through an n-type MOS transistor N1 which forms a primary side of a current mirror. Another current flowing through a p-type MOS transistor P2 and an n-type MOS transistor N3 which form a secondary side of the current mirror is defined depending upon the current flowing through the n-type MOS transistor N1. The current flowing through the p-type MOS transistor P2 and the n-type MOS transistor N3 is supplied as an operating current of a ring oscillator comprising inverters I1˜I3. Accordingly, a cycle (timer cycle) of a clock signal CLK outputted from this ring oscillator reflects a temperature characteristic of the diode D, wherein the timer cycle is decreased with increasing the temperature.

Abstract: An operation control circuit is provided for shortening a transition time from a deep stand-by mode to a stand-by mode in a pseudo-SRAM having the deep stand-by mode and the stand-by mode. The transition from the deep stand-by mode to the stand-by mode starts first and second timer circuits 12 and 14 which respectively output a timer output TN of a constant cycle needed for self-refresh and a timing signal TR of a shorter cycle than a self-refresh cycle. A counter circuit 15 counts the output TR from the second timer circuit 14 immediately after the deep stand-by mode has been transitioned to the stand-by mode. If the counted value corresponds to a value as set, then the counter circuit 15 outputs an operation mode switching signal C. A selector circuit 17 comprising a multiplexer is switched and controlled by the output from the counter circuit 15.

Abstract: A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit (4) receives change of an address (“Address”), and generates a one shot pulse in an address transition detect signal (ATD) after an address skew period has elapsed. In the case of a write request, a write enable signal (/WE) is dropped within the address skew period. First, writing or reading is performed from the rising edge of the one shot pulse, and, in the case of writing, late writing is performed using the address and the data which were presented at the time of the directly preceding write request. Next, refresh is performed during the period from the falling edge of the one shot pulse until the address skew period of the subsequent memory cycle is completed.

Abstract: A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors 3C, 4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit 3 and a boost circuit 4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit 3 and the boost circuit 4.

Abstract: A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit (4) receives change of an address (“Address”), and generates a one shot pulse in an address transition detect signal (ATD) after an address skew period has elapsed. In the case of a write request, a write enable signal (/WE) is dropped within the address skew period. First, writing or reading is performed from the rising edge of the one shot pulse, and, in the case of writing, late writing is performed using the address and the data which were presented at the time of the directly preceding write request. Next, refresh is performed during the period from the falling edge of the one shot pulse until the address skew period of the subsequent memory cycle is completed.

Abstract: An image forming apparatus is provided which includes a sheet containing section for containing sheets, a conveying member and a conveying path for conveying the sheets, at least one optical sensor that is arranged in the conveying path and has a light emitting element and a light receiving element for detecting presence or absence of a sheet on the conveying path, a driver for changing an amount of emitted light of the optical sensor, a sheet supply operation detecting section for detecting a supply operation of the sheets contained in the sheet containing section, and a control section for adjusting an amount of emitted light of the optical sensor according to an output of the sheet supply operation detecting section.

Abstract: Disclosed are a frequency modulation apparatus and a frequency modulation method for generating an image clock that is used for turning on/off a laser beam that scans an image bearing member, such as a photosensitive drum. The frequency modulation apparatus divides, into a plurality of segments for each pixel, a main scan line on an image bearing member, and calculates auxiliary clock periods based on a reference clock period and variable-magnification coefficients corresponding to the segments. Then, the frequency modulation apparatus generates image clocks for the respective segments based on an initial predesignated period value and the obtained auxiliary clock periods. Furthermore, the frequency modulation apparatus includes a detecting device for detecting a difference between a reference value stored in a memory and an actual laser irradiation location, and corrects a shift in the laser irradiation location in accordance with the detection results obtained by the detecting device.

Abstract: The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit 110 holds data having been read out of memory cells in a memory cell array 106 designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1 included in the address, a multiplexer 111 sequentially and non-synchronously feeds out the data held in the data latch circuit 110 based on the column addresses A0, A1.

Abstract: A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit 101 detects this address transition. Upon receipt of a result of detection by the address transition detector circuit 101, a state control circuit 102 judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.

Abstract: A semiconductor memory device is provided, which is capable of effectively reducing a current comsumption caused by a self-refresh operation in a stand-by mode.

Abstract: The present invention is to provide a gene having asymmetric hydrolase activity which is useful for synthesis of an optically active carboxylic acid, its antipode ester, and lactone, and a hydroxycarboxylic ester asymmetric hydrolase enzyme (EnHCH) derived from Enterobacter sp. DS-S-75 strain (FERM BP-5494) which is bacteria belonging to the genus Enterobacter, a EnHCH gene shown by base sequence of SEQ.ID.NO: 1, a gene encoding a protein having an amino acid sequence of SEQ.ID.NO: 2, and E. coli DH5&agr; (pKK-EnHCH) deposited to International Patent Organism Depositary, National Institute of Advanced Industrial Science and Technology as a deposition No. FERM BP-08466.

Abstract: A semiconductor memory device capable of accelerating address access and shortening cycle time is provided. A first address decoder (2) and first refresh address decoder (5) respectively decode an external address (Xn) supplied from outside the semiconductor memory device and a refresh address (RXn) used for refreshing within the semiconductor memory device. A multiplexer (8) selects the external address side decode signal (XnDm) or the refresh address side decode signal (XnRm) and outputs the signal as a decode signal (XnMm) based on an external address transmission signal (EXTR) and refresh address transmission signal (RFTR) so that a refresh operation and a read/write operation is performed continuously within one memory cycle. A word driver (10) then decodes decode signals (XnMm, XpMq) selected with multiplexer (8) and so forth, and activates a word line (WLmq).

Abstract: A process for preparation of (R)-1,2-propanediol which comprises cultivating a microorganism belonging to genus Pseudomonas or genus Alcaligenes which has ability to assimilate (S)-1,2-propanediol as a single carbon source, in a culture medium containing racemic 1,2-propanediol as a single carbon source and then isolating the remaining (R)-1,2-propanediol from the culture broth.

Abstract: The quantity of light of an optical sensor including a light emission portion and a light reception portion is adjusted through calculation before sheet detection is performed. In order to perform the light quantity adjustment, a voltage to be applied to the light emission portion of the optical sensor is obtained by performing calculation based on a relation between a voltage applied to the light emission portion before the adjustment and an output from the light reception portion before the adjustment. Then, it is judged whether the obtained voltage exists within a predetermined range and, if a positive result is obtained, the light quantity adjustment is ended. Further, a signal requesting the cleaning of the optical sensor is outputted in accordance with a value of the obtained voltage.

Abstract: A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S0, S1 are divided into respective four blocks B0˜B3 and B10˜B13. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.

Abstract: Indium phosphor (InP) Gunn diode that realizes improvements in thermal characteristics, yield factor of good products and easy assembly to planar circuits is provided. In a Gunn diode of the present invention, contact layers are interposing an active layer. An anode electrode and a cathode electrode are formed on the uppermost contact layer. A high resistance region around the cathode electrode is formed at least in an uppermost contact layer by ion implantation using the cathode and anode electrode as a mask. A region under the cathode electrode functions as a Gunn diode and a region under the anode electrode function as a conductive path from the anode electrode to the active layer. These two regions are defined by the high resistance region.

Abstract: There are provided a voltage level control circuit with a reduced power comsumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes “H” level, a latch signal La outputted from a latch (11) becomes “H” level, whereby NFETs (14, 17, 24) turn ON. A voltage dividing circuit comprising resistances (12, 13) and current mirror differential amplifiers (20, 27) are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref2, a voltage V2 becomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch (11) is made through.