Patents by Inventor Atsushi Nozoe
Atsushi Nozoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7581058Abstract: A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside.Type: GrantFiled: December 24, 2007Date of Patent: August 25, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Keiichi Yoshida, Takashi Horii, Atsushi Nozoe, Takayuki Tamura, Tomoyuki Fujisawa, Ken Matsubara
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Patent number: 7463533Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.Type: GrantFiled: November 29, 2006Date of Patent: December 9, 2008Assignee: Renesas Technology Corp.Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
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Publication number: 20080098190Abstract: A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside.Type: ApplicationFiled: December 24, 2007Publication date: April 24, 2008Inventors: Yoshinori Takase, Keiichi Yoshida, Takashi Horii, Atsushi Nozoe, Takayuki Tamura, Tomoyuki Fujisawa, Ken Matsubara
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Patent number: 7334080Abstract: A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside.Type: GrantFiled: November 15, 2002Date of Patent: February 19, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Stystems Co., Ltd.Inventors: Yoshinori Takase, Keiichi Yoshida, Takashi Horii, Atsushi Nozoe, Takayuki Tamura, Tomoyuki Fujisawa, Ken Matsubara
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Patent number: 7290109Abstract: A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.Type: GrantFiled: January 9, 2002Date of Patent: October 30, 2007Assignee: Renesas Technology Corp.Inventors: Takashi Horii, Keiichi Yoshida, Atsushi Nozoe
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Patent number: 7283400Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.Type: GrantFiled: September 19, 2005Date of Patent: October 16, 2007Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd., Hitachi Ulsi Systems Co., Ltd.Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
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Publication number: 20070198770Abstract: A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.Type: ApplicationFiled: March 29, 2007Publication date: August 23, 2007Inventors: Takashi Horii, Keiichi Yoshida, Atsushi Nozoe
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Publication number: 20070076490Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.Type: ApplicationFiled: November 29, 2006Publication date: April 5, 2007Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
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Patent number: 7072225Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: GrantFiled: June 29, 2005Date of Patent: July 4, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Patent number: 6992936Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: GrantFiled: February 12, 2004Date of Patent: January 31, 2006Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Publication number: 20060013032Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.Type: ApplicationFiled: September 19, 2005Publication date: January 19, 2006Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
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Publication number: 20050237803Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: ApplicationFiled: June 29, 2005Publication date: October 27, 2005Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Publication number: 20050228962Abstract: A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside.Type: ApplicationFiled: November 15, 2002Publication date: October 13, 2005Inventors: Yoshinori Takase, Keiichi Yoshida, Takashi Horii, Atsushi Nozoe, Takayuki Tamura, Tomoyuki Fujisawa, Ken Matsubara
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Patent number: 6930924Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: GrantFiled: April 2, 2003Date of Patent: August 16, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Publication number: 20050015539Abstract: A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.Type: ApplicationFiled: January 9, 2002Publication date: January 20, 2005Inventors: Takashi Horii, Keiichi Yoshida, Atsushi Nozoe
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Publication number: 20040210729Abstract: A nonvolatile memory, provided with nonvolatile memory cells, has a plurality of memory banks each of which can perform memory operations independently of others, and a control unit for controlling the memory operations of the memory banks. The control unit is capable of controlling an interleave operation by which, even during a memory operation in response to an operational instruction designating one of the memory banks, a memory operation in response to another operational instruction designating another memory bank can be started, and a parallel operation by which both memory banks are caused to perform memory operations in parallel when, before a memory operation in response to an operational instruction designating one of the memory banks is started, another memory operation designating another memory bank is instructed. Each memory bank is provided with a status register, and the status of memory operation in each memory bank is reflected in the corresponding status register.Type: ApplicationFiled: January 23, 2004Publication date: October 21, 2004Applicant: Renesas Technology Corp.Inventors: Takashi Horii, Keiichi Yoshida, Atsushi Nozoe
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Publication number: 20040160829Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: ApplicationFiled: February 12, 2004Publication date: August 19, 2004Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Publication number: 20040145939Abstract: In a method for producing non-volatile semiconductor storage devices, a non-volatile semiconductor storage devices comprises a memory array (10) that includes a plurality of non-volatile storage elements and a plurality of spare storage elements, each of which enables information to be written/erased therein/therefrom electrically, and a storage element, if it is decided to be defective during a write operation, is replaced with one of the spare storage elements (10a), and information related to the defective storage element is stored in a predetermined area (10b) provided in the memory array. In the method, if the defective storage element is detected by a test, the information related to each detected defective storage element is not stored in the predetermined area of the memory array, and the one in which a rate of the defective storage elements detected by the test is under a predetermined value is extracted as a non-defective product.Type: ApplicationFiled: November 19, 2003Publication date: July 29, 2004Inventors: Keichi Yoshida, Atsushi Nozoe
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Patent number: 6721207Abstract: A non-volatile memory system is provided with a control device and non-volatile memory devices, each including memory cells and data latches. The control device supplies commands to the non-volatile memory devices, including a write command, and first and second read commands. When the control device supplies the write command with write address information and data for storing in the non-volatile memory device, it stores the data to the data latches and then to the memory cells, and then verifies storage. When the control device supplies the first read command with read address information, the nonvolatile memory device reads data stored in the memory cells to the data latches and then outputs the data in the data latches to the control device. When the control device supplies the second read command, the non-volatile memory device outputs data in the data latches to the control device.Type: GrantFiled: August 5, 2002Date of Patent: April 13, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6711054Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: GrantFiled: November 19, 2002Date of Patent: March 23, 2004Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake