Patents by Inventor Atsushi Nozoe
Atsushi Nozoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030202392Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: ApplicationFiled: April 2, 2003Publication date: October 30, 2003Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Patent number: 6567315Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: GrantFiled: December 12, 2001Date of Patent: May 20, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Publication number: 20030072202Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: ApplicationFiled: November 19, 2002Publication date: April 17, 2003Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Patent number: 6549460Abstract: A nonvolatile memory device having an error correcting function, capable of outputting read-out data (uncorrected) while simultaneously generating syndromes. After the syndrome formation, the memory device outputs an error status signal (ERR) and, depending on the presence or absence of an externally supplied request (SC), again outputs read-out data (this time corrected).Type: GrantFiled: December 12, 2001Date of Patent: April 15, 2003Assignee: Hitachi, Ltd.Inventors: Atsushi Nozoe, Kazuo Nakamura, Kunihiro Katayama
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Patent number: 6507520Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: GrantFiled: December 11, 2001Date of Patent: January 14, 2003Assignee: Hitachi, Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6504764Abstract: A non-volatile memory device having a plurality of memory cells and a control circuit. The control circuit receives operation commands from outside the device and controls the operation of the device according to the commands. The commands include read commands and write commands. In a read command, the control circuit reads data in the memory cells and outputs it. In a write command, the control circuit controls the inputting of data to data latch circuits and then to memory cells. The control circuit provides status information indicating whether the writing of data is a success or a failure.Type: GrantFiled: November 1, 2001Date of Patent: January 7, 2003Assignee: Hitachi, Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Publication number: 20020191459Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: ApplicationFiled: August 5, 2002Publication date: December 19, 2002Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6496418Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: GrantFiled: November 1, 2001Date of Patent: December 17, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Patent number: 6490195Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: GrantFiled: October 1, 2001Date of Patent: December 3, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Patent number: 6459621Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: GrantFiled: August 17, 2001Date of Patent: October 1, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Engineering CorporationInventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Patent number: 6456526Abstract: A non-volatile memory device having a plurality of memory cells and a control circuit. The control circuit receives operation commands from outside the device and controls the operation of the device according to the commands. The commands include read commands and write commands. In the read command the control circuit reads data in the memory cells and outputs it. In a write command the control circuit controls the inputting of data to data latch circuits and then to memory cells. The control circuit provides status information indicating whether the writing of data is a success or a failure.Type: GrantFiled: March 30, 2001Date of Patent: September 24, 2002Assignee: Hitachi, Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Publication number: 20020114192Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: ApplicationFiled: December 12, 2001Publication date: August 22, 2002Applicant: Hitachi, Ltd.Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Publication number: 20020054508Abstract: A nonvolatile memory device having an error correcting function, capable of outputting read-out data (uncorrected) while simultaneously generating syndromes. After the syndrome formation, the memory device outputs an error status signal (ERR) and, depending on the presence or absence of an externally supplied request (SC), again outputs read-out data (this time corrected).Type: ApplicationFiled: December 12, 2001Publication date: May 9, 2002Inventors: Atsushi Nozoe, Kazuo Nakamura, Kunihiro Katayama
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Publication number: 20020044485Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: ApplicationFiled: December 11, 2001Publication date: April 18, 2002Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6359806Abstract: A nonvolatile memory device having an error correcting function, capable of outputting read-out data (uncorrected) while simultaneously generating syndromes. After the syndrome formation, the memory device outputs an error status signal (ERR) and, depending on the presence or absence of an externally supplied request (SC), again outputs read-out data (this time corrected).Type: GrantFiled: April 26, 2000Date of Patent: March 19, 2002Assignee: Hitachi, Ltd.Inventors: Atsushi Nozoe, Kazuo Nakamura, Kunihiro Katayama
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Publication number: 20020027807Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: ApplicationFiled: November 1, 2001Publication date: March 7, 2002Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Publication number: 20020024846Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: ApplicationFiled: November 1, 2001Publication date: February 28, 2002Inventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Patent number: 6351412Abstract: A nonvolatile memory device having an error correcting function, capable of outputting read-out data (uncorrected) while simultaneously generating syndromes. After the syndrome formation, the memory device outputs an error status signal (ERR) and, depending on the presence or absence of an externally supplied request (SC), again outputs read-out data (this time corrected).Type: GrantFiled: August 11, 2000Date of Patent: February 26, 2002Assignee: Hitachi, Ltd.Inventors: Atsushi Nozoe, Kazuo Nakamura, Kunihiro Katayama
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Publication number: 20020008991Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: ApplicationFiled: October 1, 2001Publication date: January 24, 2002Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Publication number: 20020001231Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell-is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: ApplicationFiled: March 30, 2000Publication date: January 3, 2002Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamaoto, Ken Matsubara